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Add missing test case for r141410.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141498 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-10-08 18:06:54 +00:00
parent 70b582ab9c
commit a55f6575ae
1 changed files with 39 additions and 0 deletions
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39
test/CodeGen/X86/norex-subreg.ll Normal file
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; RUN: llc -O0 < %s
target triple = "x86_64-apple-macosx10.7"
; This test case extracts a sub_8bit_hi sub-register:
;
; %R8B<def> = COPY %BH, %EBX<imp-use,kill>
; %ESI<def> = MOVZX32_NOREXrr8 %R8B<kill>
;
; The register allocation above is invalid, %BH can only be encoded without an
; REX prefix, so the destination register must be GR8_NOREX. The code above
; triggers an assertion in copyPhysReg.
;
; <rdar://problem/10248099>
define void @f() nounwind uwtable ssp {
entry:
%0 = load i32* undef, align 4
%add = add i32 0, %0
%conv1 = trunc i32 %add to i16
%bf.value = and i16 %conv1, 255
%1 = and i16 %bf.value, 255
%2 = shl i16 %1, 8
%3 = load i16* undef, align 1
%4 = and i16 %3, 255
%5 = or i16 %4, %2
store i16 %5, i16* undef, align 1
%6 = load i16* undef, align 1
%7 = lshr i16 %6, 8
%bf.clear2 = and i16 %7, 255
%conv3 = zext i16 %bf.clear2 to i32
%rem = srem i32 %conv3, 15
%conv4 = trunc i32 %rem to i16
%bf.value5 = and i16 %conv4, 255
%8 = and i16 %bf.value5, 255
%9 = shl i16 %8, 8
%10 = or i16 undef, %9
store i16 %10, i16* undef, align 1
ret void
}