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[mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not available on MIPS32r6/MIPS64r6

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Summary:
This patch updates both the assembler and the code generator.

MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused
multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted.

Depends on D3955

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3956

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210763 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-06-12 11:04:18 +00:00
parent d94bc707c4
commit a61aa38ee1
5 changed files with 322 additions and 45 deletions
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1
lib/Target/Mips/Mips32r6InstrInfo.td
View File

@ -35,7 +35,6 @@ include "Mips32r6InstrFormats.td"
// Removed: ldxc1
// Removed: luxc1
// Removed: lwxc1
// Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
// Removed: movf, movt
// Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
// Removed: movn, movz

24
lib/Target/Mips/MipsInstrFPU.td
View File

@ -457,42 +457,42 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM<4, 0>, ISA_MIPS32R2;
MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM<5, 0>, ISA_MIPS32R2;
MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
let AdditionalPredicates = [NoNaNsFPMath] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM<6, 0>, ISA_MIPS32R2;
MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM<7, 0>, ISA_MIPS32R2;
MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
}
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, ISA_MIPS32R2, FGR_32;
MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>, ISA_MIPS32R2, FGR_32;
MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
let AdditionalPredicates = [NoNaNsFPMath] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, ISA_MIPS32R2, FGR_32;
MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, ISA_MIPS32R2, FGR_32;
MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
}
let isCodeGenOnly=1 in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, ISA_MIPS32R2, FGR_64;
MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>, ISA_MIPS32R2, FGR_64;
MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
}
let AdditionalPredicates = [NoNaNsFPMath],
isCodeGenOnly=1 in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, ISA_MIPS32R2, FGR_64;
MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, ISA_MIPS32R2, FGR_64;
MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
}
//===----------------------------------------------------------------------===//

3
lib/Target/Mips/MipsInstrInfo.td
View File

@ -236,6 +236,9 @@ class ISA_MIPS32_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
}
class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
class ISA_MIPS32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
}
class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }

324
test/CodeGen/Mips/fmadd1.ll
View File

@ -5,15 +5,54 @@
; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only
; available when -enable-no-nans-fp-math is given.
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefix=32R2 -check-prefix=CHECK
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=64R2 -check-prefix=CHECK
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2NAN -check-prefix=CHECK
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2NAN -check-prefix=CHECK
; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NONAN
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NONAN
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NONAN
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64 -check-prefix=64-NONAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NONAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NONAN
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NAN
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NAN
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NAN
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64 -check-prefix=64-NAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NAN
define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
entry:
; CHECK-LABEL: FOO0float:
; CHECK: madd.s
; ALL-LABEL: FOO0float:
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: add.s $f0, $[[T1]], $[[T2]]
; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2: add.s $f0, $[[T1]], $[[T2]]
; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2: add.s $f0, $[[T0]], $[[T1]]
; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
; 64R6-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]]
%mul = fmul float %a, %b
%add = fadd float %mul, %c
%add1 = fadd float %add, 0.000000e+00
@ -22,8 +61,39 @@ entry:
define float @FOO1float(float %a, float %b, float %c) nounwind readnone {
entry:
; CHECK-LABEL: FOO1float:
; CHECK: msub.s
; ALL-LABEL: FOO1float:
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: add.s $f0, $[[T1]], $[[T2]]
; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2: add.s $f0, $[[T1]], $[[T2]]
; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2: add.s $f0, $[[T0]], $[[T1]]
; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
; 64R6-DAG: sub.s $[[T1:f[0-9]+]], $[[T0]], $f14
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]]
%mul = fmul float %a, %b
%sub = fsub float %mul, %c
%add = fadd float %sub, 0.000000e+00
@ -32,11 +102,44 @@ entry:
define float @FOO2float(float %a, float %b, float %c) nounwind readnone {
entry:
; CHECK-LABEL: FOO2float:
; 32R2: nmadd.s
; 64R2: nmadd.s
; 32R2NAN: madd.s
; 64R2NAN: madd.s
; ALL-LABEL: FOO2float:
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
%mul = fmul float %a, %b
%add = fadd float %mul, %c
%sub = fsub float 0.000000e+00, %add
@ -45,11 +148,36 @@ entry:
define float @FOO3float(float %a, float %b, float %c) nounwind readnone {
entry:
; CHECK-LABEL: FOO3float:
; 32R2: nmsub.s
; 64R2: nmsub.s
; 32R2NAN: msub.s
; 64R2NAN: msub.s
; ALL-LABEL: FOO3float:
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
%mul = fmul float %a, %b
%sub = fsub float %mul, %c
%sub1 = fsub float 0.000000e+00, %sub
@ -58,8 +186,40 @@ entry:
define double @FOO10double(double %a, double %b, double %c) nounwind readnone {
entry:
; CHECK-LABEL: FOO10double:
; CHECK: madd.d
; ALL-LABEL: FOO10double:
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: add.d $f0, $[[T1]], $[[T2]]
; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2: mtc1 $zero, $[[T2:f[02468]+]]
; 32R2: mtc1 $zero, ${{f[13579]+}}
; 32R2: add.d $f0, $[[T1]], $[[T2]]
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2: add.d $f0, $[[T0]], $[[T1]]
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]]
%mul = fmul double %a, %b
%add = fadd double %mul, %c
%add1 = fadd double %add, 0.000000e+00
@ -68,8 +228,40 @@ entry:
define double @FOO11double(double %a, double %b, double %c) nounwind readnone {
entry:
; CHECK-LABEL: FOO11double:
; CHECK: msub.d
; ALL-LABEL: FOO11double:
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: add.d $f0, $[[T1]], $[[T2]]
; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2: mtc1 $zero, $[[T2:f[02468]+]]
; 32R2: mtc1 $zero, ${{f[13579]+}}
; 32R2: add.d $f0, $[[T1]], $[[T2]]
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2: add.d $f0, $[[T0]], $[[T1]]
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]]
%mul = fmul double %a, %b
%sub = fsub double %mul, %c
%add = fadd double %sub, 0.000000e+00
@ -78,11 +270,45 @@ entry:
define double @FOO12double(double %a, double %b, double %c) nounwind readnone {
entry:
; CHECK-LABEL: FOO12double:
; 32R2: nmadd.d
; 64R2: nmadd.d
; 32R2NAN: madd.d
; 64R2NAN: madd.d
; ALL-LABEL: FOO12double:
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $zero, $[[T2:f[02468]+]]
; 32R2-NAN: mtc1 $zero, ${{f[13579]+}}
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
%mul = fmul double %a, %b
%add = fadd double %mul, %c
%sub = fsub double 0.000000e+00, %add
@ -91,11 +317,45 @@ entry:
define double @FOO13double(double %a, double %b, double %c) nounwind readnone {
entry:
; CHECK-LABEL: FOO13double:
; 32R2: nmsub.d
; 64R2: nmsub.d
; 32R2NAN: msub.d
; 64R2NAN: msub.d
; ALL-LABEL: FOO13double:
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $zero, $[[T2:f[02468]+]]
; 32R2-NAN: mtc1 $zero, ${{f[13579]+}}
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
%mul = fmul double %a, %b
%sub = fsub double %mul, %c
%sub1 = fsub double 0.000000e+00, %sub

15
test/MC/Mips/mips32r6/invalid-mips32r2.s Normal file
View File

@ -0,0 +1,15 @@
# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled