Add instruction encodings / disassembler support for 2rus instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

@@ -137,6 +137,16 @@ static DecodeStatus Decode3RInstruction(MCInst &Inst,
                                         uint64_t Address,
                                         const void *Decoder);
 
+static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
+                                          unsigned Insn,
+                                          uint64_t Address,
+                                          const void *Decoder);
+
+static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
+                                              unsigned Insn,
+                                              uint64_t Address,
+                                              const void *Decoder);
+
 #include "XCoreGenDisassemblerTables.inc"
 
 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@@ -202,6 +212,12 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
   // Try and decode as a 3R instruction.
   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
   switch (Opcode) {
+  case 0x0:
+    Inst.setOpcode(XCore::STW_2rus);
+    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+  case 0x1:
+    Inst.setOpcode(XCore::LDW_2rus);
+    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
   case 0x2:
     Inst.setOpcode(XCore::ADD_3r);
     return Decode3RInstruction(Inst, Insn, Address, Decoder);
@@ -232,6 +248,21 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
   case 0x11:
     Inst.setOpcode(XCore::LD8U_3r);
     return Decode3RInstruction(Inst, Insn, Address, Decoder);
+  case 0x12:
+    Inst.setOpcode(XCore::ADD_2rus);
+    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+  case 0x13:
+    Inst.setOpcode(XCore::SUB_2rus);
+    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+  case 0x14:
+    Inst.setOpcode(XCore::SHL_2rus);
+    return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+  case 0x15:
+    Inst.setOpcode(XCore::SHR_2rus);
+    return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+  case 0x16:
+    Inst.setOpcode(XCore::EQ_2rus);
+    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
   case 0x18:
     Inst.setOpcode(XCore::LSS_3r);
     return Decode3RInstruction(Inst, Insn, Address, Decoder);
@@ -361,6 +392,32 @@ Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
   return S;
 }
 
+static DecodeStatus
+Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+                      const void *Decoder) {
+  unsigned Op1, Op2, Op3;
+  DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
+  if (S == MCDisassembler::Success) {
+    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+    Inst.addOperand(MCOperand::CreateImm(Op3));
+  }
+  return S;
+}
+
+static DecodeStatus
+Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+                      const void *Decoder) {
+  unsigned Op1, Op2, Op3;
+  DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
+  if (S == MCDisassembler::Success) {
+    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+    DecodeBitpOperand(Inst, Op3, Address, Decoder);
+  }
+  return S;
+}
+
 MCDisassembler::DecodeStatus
 XCoreDisassembler::getInstruction(MCInst &instr,
                                   uint64_t &Size,

lib/Target/XCore/XCoreInstrFormats.td

@@ -43,8 +43,17 @@ class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
     : InstXCore<4, outs, ins, asmstr, pattern> {
 }
 
-class _F2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
+class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
     : InstXCore<2, outs, ins, asmstr, pattern> {
+  let Inst{15-11} = opc;
+  let DecoderMethod = "Decode2RUSInstruction";
+}
+
+// 2RUS with bitp operand
+class _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr,
+                 list<dag> pattern>
+    : _F2RUS<opc, outs, ins, asmstr, pattern> {
+  let DecoderMethod = "Decode2RUSBitpInstruction";
 }
 
 class _FL2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>

lib/Target/XCore/XCoreInstrInfo.td

@@ -200,30 +200,30 @@ def InlineJT32 : Operand<i32> {
 
 // Three operand short
 
-multiclass F3R_2RUS<bits<5> opc, string OpcStr, SDNode OpNode> {
+multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
-  def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
+  def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
                 !strconcat(OpcStr, " $dst, $b, $c"),
                 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
-  def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
+  def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
                      !strconcat(OpcStr, " $dst, $b, $c"),
                      [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
 }
 
-multiclass F3R_2RUS_np<bits<5> opc, string OpcStr> {
+multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
-  def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
+  def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
                 !strconcat(OpcStr, " $dst, $b, $c"), []>;
-  def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
+  def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
                      !strconcat(OpcStr, " $dst, $b, $c"), []>;
 }
 
-multiclass F3R_2RBITP<bits<5> opc, string OpcStr, SDNode OpNode> {
+multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
-  def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
+                      SDNode OpNode> {
+  def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
                 !strconcat(OpcStr, " $dst, $b, $c"),
                 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
-  def _2rus : _F2RUS<
+  def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
-                 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
+                         !strconcat(OpcStr, " $dst, $b, $c"),
-                 !strconcat(OpcStr, " $dst, $b, $c"),
+                         [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
-                 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
 }
 
 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
@@ -382,10 +382,10 @@ let usesCustomInserter = 1 in {
 //===----------------------------------------------------------------------===//
 
 // Three operand short
-defm ADD : F3R_2RUS<0b00010, "add", add>;
+defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
-defm SUB : F3R_2RUS<0b00011, "sub", sub>;
+defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
 let neverHasSideEffects = 1 in {
-defm EQ : F3R_2RUS_np<0b00110, "eq">;
+defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
 def LSS_3r : F3R_np<0b11000, "lss">;
 def LSU_3r : F3R_np<0b11001, "lsu">;
 }
@@ -397,9 +397,9 @@ def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
                   (ins GRRegs:$addr, GRRegs:$offset),
                   "ldw $dst, $addr[$offset]", []>;
 
-def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
+def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
-                  "ldw $dst, $addr[$offset]",
+                      (ins GRRegs:$addr, i32imm:$offset),
-                  []>;
+                      "ldw $dst, $addr[$offset]", []>;
 
 def LD16S_3r :  _F3R<0b10000, (outs GRRegs:$dst),
                      (ins GRRegs:$addr, GRRegs:$offset),
@@ -414,12 +414,13 @@ let mayStore=1 in {
 def STW_3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
                     "stw $val, $addr[$offset]", []>;
 
-def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
+def STW_2rus : _F2RUS<0b0000, (outs),
-                  "stw $val, $addr[$offset]", []>;
+                      (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
+                      "stw $val, $addr[$offset]", []>;
 }
 
-defm SHL : F3R_2RBITP<0b00100, "shl", shl>;
+defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
-defm SHR : F3R_2RBITP<0b00101, "shr", srl>;
+defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
 // TODO tsetr
 
 // Three operand long

test/MC/Disassembler/XCore/xcore.txt

@@ -234,3 +234,26 @@
 
 # CHECK: sub r4, r2, r5
 0x89 0x1a
+
+# 2rus instructions
+
+# CHECK: add r10, r2, 5
+0xe9 0x92
+
+# CHECK: eq r2, r1, 0
+0x24 0xb0
+
+# CHECK: ldw r5, r6[1]
+0x19 0x09
+
+# CHECK: shl r6, r5, 24
+0xa6 0xa5
+
+# CHECK: shr r3, r8, 5
+0xf1 0xab
+
+# CHECK: stw r3, r2[0]
+0x38 0x00
+
+# CHECK: sub r2, r4, 11
+0x63 0x9d