RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-02-04 01:26:41 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Mark instruction classes ArithLogicR, ArithLogicI and LoadUpper as isRematerializable.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155031 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-04-18 18:52:10 +00:00
parent 9853b49f61
commit a69534912d
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/Mips/MipsInstrInfo.td
View File

@ -315,6 +315,7 @@ class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
[(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
let shamt = 0;
let isCommutable = isComm;
let isReMaterializable = 1;
}
class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
@ -330,7 +331,9 @@ class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
Operand Od, PatLeaf imm_type, RegisterClass RC> :
FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
!strconcat(instr_asm, "\t$rt, $rs, $imm16"),
[(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
[(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
let isReMaterializable = 1;
}
class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
Operand Od, PatLeaf imm_type, RegisterClass RC> :
@ -386,6 +389,7 @@ class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
let rs = 0;
let neverHasSideEffects = 1;
let isReMaterializable = 1;
}
class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,