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Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
Add an extra run with -regalloc=basic to keep them honest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
1d6b38d9d3
commit
a6f7499244
@ -1,4 +1,9 @@
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; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2
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; RUN: llc < %s -march=mips -regalloc=linearscan | grep {subu.*sp} | count 2
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; This test depends on a linearscan optimization, joining copies from reserved
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; registers.
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; After coalescing, copies from %SP remain.
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; They are handled by RALinScan::attemptTrivialCoalescing
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "mipsallegrexel-unknown-psp-elf"
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s
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; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
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; Fix PR7473
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define i32 @main() nounwind readnone {
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@ -9,12 +10,12 @@ entry:
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volatile store i32 0, i32* %c, align 4
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%0 = volatile load i32* %a, align 4 ; <i32> [#uses=1]
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%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
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; CHECK: addiu $4, $zero, 0
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; CHECK: addiu $[[R1:[0-9]+]], $zero, 0
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%iftmp.0.0 = select i1 %1, i32 3, i32 0 ; <i32> [#uses=1]
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%2 = volatile load i32* %c, align 4 ; <i32> [#uses=1]
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%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
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; CHECK: addiu $4, $zero, 3
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; CHECK: addu $2, $3, $4
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; CHECK: addiu $[[R1]], $zero, 3
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; CHECK: addu $2, ${{.}}, $[[R1]]
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%iftmp.2.0 = select i1 %3, i32 0, i32 5 ; <i32> [#uses=1]
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%4 = add nsw i32 %iftmp.2.0, %iftmp.0.0 ; <i32> [#uses=1]
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ret i32 %4
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@ -1,10 +1,11 @@
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; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
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; RUN: llc -march=mips -mcpu=4ke -regalloc=basic < %s | FileCheck %s
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@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
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@i3 = common global i32* null, align 4
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; CHECK: lw $3, %got(i3)($gp)
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; CHECK: addiu $5, $gp, %got(i1)
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; CHECK: lw ${{[0-9]+}}, %got(i3)($gp)
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; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1)
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define i32* @cmov1(i32 %s) nounwind readonly {
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entry:
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%tobool = icmp ne i32 %s, 0
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@ -1,4 +1,5 @@
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; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s
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; All test functions do the same thing - they return the first variable
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@ -56,14 +57,14 @@ entry:
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; CHECK: va2:
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; CHECK: addiu $sp, $sp, -40
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; CHECK: addiu $2, $sp, 44
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; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
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; CHECK: sw $5, 44($sp)
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; CHECK: sw $6, 48($sp)
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; CHECK: sw $7, 52($sp)
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; CHECK: addiu $3, $2, 7
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; CHECK: addiu $5, $zero, -8
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; CHECK: and $3, $3, $5
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; CHECK: ldc1 $f0, 0($3)
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; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
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; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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; CHECK: ldc1 $f0, 0($[[R3]])
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}
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; int
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@ -109,11 +110,11 @@ entry:
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; CHECK: addiu $sp, $sp, -48
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; CHECK: sw $6, 56($sp)
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; CHECK: sw $7, 60($sp)
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; CHECK: addiu $3, $sp, 56
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; CHECK: addiu $6, $3, 7
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; CHECK: addiu $7, $zero, -8
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; CHECK: and $2, $6, $7
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; CHECK: ldc1 $f0, 0($2)
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; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
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; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
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; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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; CHECK: ldc1 $f0, 0($[[R3]])
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}
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; int
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@ -165,11 +166,11 @@ entry:
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; CHECK: va6:
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; CHECK: addiu $sp, $sp, -48
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; CHECK: sw $7, 60($sp)
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; CHECK: addiu $2, $sp, 60
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; CHECK: addiu $3, $2, 7
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; CHECK: addiu $4, $zero, -8
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; CHECK: and $3, $3, $4
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; CHECK: ldc1 $f0, 0($3)
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; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
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; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
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; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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; CHECK: ldc1 $f0, 0($[[R3]])
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}
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; int
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@ -215,11 +216,11 @@ entry:
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; CHECK: va8:
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; CHECK: addiu $sp, $sp, -48
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; CHECK: addiu $3, $sp, 64
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; CHECK: addiu $4, $3, 7
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; CHECK: addiu $5, $zero, -8
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; CHECK: and $2, $4, $5
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; CHECK: ldc1 $f0, 0($2)
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; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
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; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
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; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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; CHECK: ldc1 $f0, 0($[[R3]])
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}
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; int
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@ -269,9 +270,9 @@ entry:
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; CHECK: va10:
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; CHECK: addiu $sp, $sp, -56
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; CHECK: addiu $3, $sp, 76
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; CHECK: addiu $2, $3, 7
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; CHECK: addiu $4, $zero, -8
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; CHECK: and $2, $2, $4
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; CHECK: ldc1 $f0, 0($2)
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; CHECK: addiu $[[R0:[0-9]+]], $sp, 76
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; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
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; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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; CHECK: ldc1 $f0, 0($[[R3]])
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}
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@ -1,5 +1,7 @@
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;RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8
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;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
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;RUN: llc -march=sparc -regalloc=linearscan < %s | FileCheck %s -check-prefix=V8
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;RUN: llc -march=sparc -regalloc=linearscan -mattr=v9 < %s | FileCheck %s -check-prefix=V9
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; These tests depend on linear scan's trivial coalescer for reserved registers.
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define i8* @frameaddr() nounwind readnone {
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entry:
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=xcore | FileCheck %s
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; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s
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define i64 @umul_lohi(i32 %a, i32 %b) {
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entry:
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%0 = zext i32 %a to i64
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@ -7,8 +8,8 @@ entry:
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ret i64 %2
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}
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; CHECK: umul_lohi:
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; CHECK: ldc r2, 0
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; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2
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; CHECK: ldc [[REG:r[0-9]+]], 0
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; CHECK-NEXT: lmul r1, r0, r1, r0, [[REG]], [[REG]]
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; CHECK-NEXT: retsp 0
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define i64 @smul_lohi(i32 %a, i32 %b) {
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@ -19,11 +20,11 @@ entry:
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ret i64 %2
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}
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; CHECK: smul_lohi:
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; CHECK: ldc r2, 0
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; CHECK-NEXT: mov r3, r2
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; CHECK-NEXT: maccs r2, r3, r1, r0
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: mov r1, r2
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; CHECK: ldc
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; CHECK-NEXT: mov
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; CHECK-NEXT: maccs
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; CHECK-NEXT: mov r0,
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; CHECK-NEXT: mov r1,
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; CHECK-NEXT: retsp 0
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define i64 @mul64(i64 %a, i64 %b) {
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@ -32,11 +33,11 @@ entry:
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ret i64 %0
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}
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; CHECK: mul64:
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; CHECK: ldc r11, 0
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; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11
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; CHECK-NEXT: mul r0, r0, r3
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; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0
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; CHECK-NEXT: mov r0, r4
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; CHECK: ldc
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; CHECK-NEXT: lmul
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; CHECK-NEXT: mul
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; CHECK-NEXT: lmul
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; CHECK-NEXT: mov r0,
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define i64 @mul64_2(i64 %a, i32 %b) {
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entry:
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@ -45,8 +46,8 @@ entry:
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ret i64 %1
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}
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; CHECK: mul64_2:
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; CHECK: ldc r3, 0
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; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3
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; CHECK-NEXT: mul r1, r1, r2
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; CHECK-NEXT: add r1, r3, r1
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; CHECK: ldc
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; CHECK-NEXT: lmul
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; CHECK-NEXT: mul
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; CHECK-NEXT: add r1,
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; CHECK-NEXT: retsp 0
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