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R600/SI: Add verifier check for immediates in register operands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212214 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-07-02 20:53:44 +00:00
parent 7950cae7b9
commit a75d388f18
4 changed files with 33 additions and 2 deletions
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9
lib/Target/R600/SIInstrInfo.cpp
View File

@ -559,7 +559,14 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
// Make sure the register classes are correct // Make sure the register classes are correct
for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
switch (Desc.OpInfo[i].OperandType) { switch (Desc.OpInfo[i].OperandType) {
case MCOI::OPERAND_REGISTER: case MCOI::OPERAND_REGISTER: {
int RegClass = Desc.OpInfo[i].RegClass;
if (!RI.regClassCanUseImmediate(RegClass) &&
(MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
ErrInfo = "Expected register, but got immediate";
return false;
}
}
break; break;
case MCOI::OPERAND_IMMEDIATE: case MCOI::OPERAND_IMMEDIATE:
if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) { if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) {

2
lib/Target/R600/SIInstructions.td
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@ -1632,7 +1632,7 @@ let usesCustomInserter = 1 in {
// constant that can be used with the ADDR64 MUBUF instructions. // constant that can be used with the ADDR64 MUBUF instructions.
def SI_ADDR64_RSRC : InstSI < def SI_ADDR64_RSRC : InstSI <
(outs SReg_128:$srsrc), (outs SReg_128:$srsrc),
(ins SReg_64:$ptr), (ins SSrc_64:$ptr),
"", [] "", []
>; >;

16
lib/Target/R600/SIRegisterInfo.cpp
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@ -125,3 +125,19 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
unsigned Index = getHWRegIndex(Reg); unsigned Index = getHWRegIndex(Reg);
return SubRC->getRegister(Index + Channel); return SubRC->getRegister(Index + Channel);
} }
bool SIRegisterInfo::regClassCanUseImmediate(int RCID) const {
switch (RCID) {
default: return false;
case AMDGPU::SSrc_32RegClassID:
case AMDGPU::SSrc_64RegClassID:
case AMDGPU::VSrc_32RegClassID:
case AMDGPU::VSrc_64RegClassID:
return true;
}
}
bool SIRegisterInfo::regClassCanUseImmediate(
const TargetRegisterClass *RC) const {
return regClassCanUseImmediate(RC->getID());
}

8
lib/Target/R600/SIRegisterInfo.h
View File

@ -60,6 +60,14 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
/// \returns The sub-register of Reg that is in Channel. /// \returns The sub-register of Reg that is in Channel.
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
unsigned Channel) const; unsigned Channel) const;
/// \returns True if operands defined with this register class can accept
/// inline immediates.
bool regClassCanUseImmediate(int RCID) const;
/// \returns True if operands defined with this register class can accept
/// inline immediates.
bool regClassCanUseImmediate(const TargetRegisterClass *RC) const;
}; };
} // End namespace llvm } // End namespace llvm