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[mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECT
(or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b). where $mask is a constant splat. This allows bitwise operations to make use of bsel. It's also a stepping stone towards matching bins[lr], and bins[lr]i from normal IR. Two sets of similar tests have been added in this commit. The bsel_* functions test the case where binsri cannot be used. The binsr_*_i functions will start to use the binsri instruction in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193682 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
aed9334acf
commit
a7c3cac871
@ -93,6 +93,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::VSELECT);
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setTargetDAGCombine(ISD::XOR);
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@ -487,6 +488,110 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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// Determine if the specified node is a constant vector splat.
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//
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// Returns true and sets Imm if:
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// * N is a ISD::BUILD_VECTOR representing a constant splat
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//
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// This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
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// differences are that it assumes the MSA has already been checked and the
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// arbitrary requirement for a maximum of 32-bit integers isn't applied (and
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// must not be in order for binsri.d to be selectable).
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static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
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BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
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if (Node == NULL)
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return false;
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APInt SplatValue, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
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8, !IsLittleEndian))
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return false;
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Imm = SplatValue;
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return true;
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}
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// Perform combines where ISD::OR is the root node.
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//
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// Performs the following transformations:
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// - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
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// where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
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// vector type.
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static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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if (!Subtarget->hasMSA())
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return SDValue();
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EVT Ty = N->getValueType(0);
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if (!Ty.is128BitVector())
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return SDValue();
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
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SDValue Op0Op0 = Op0->getOperand(0);
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SDValue Op0Op1 = Op0->getOperand(1);
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SDValue Op1Op0 = Op1->getOperand(0);
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SDValue Op1Op1 = Op1->getOperand(1);
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bool IsLittleEndian = !Subtarget->isLittle();
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SDValue IfSet, IfClr, Cond;
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APInt Mask, InvMask;
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// If Op0Op0 is an appropriate mask, try to find it's inverse in either
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// Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
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// looking.
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// IfClr will be set if we find a valid match.
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if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
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Cond = Op0Op0;
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IfSet = Op0Op1;
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if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
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IfClr = Op1Op1;
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else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
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IfClr = Op1Op0;
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}
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// If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
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// thing again using this mask.
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// IfClr will be set if we find a valid match.
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if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
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Cond = Op0Op1;
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IfSet = Op0Op0;
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if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
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IfClr = Op1Op1;
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else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
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IfClr = Op1Op0;
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}
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// At this point, IfClr will be set if we have a valid match.
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if (!IfClr.getNode())
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return SDValue();
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assert(Cond.getNode() && IfSet.getNode());
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// Fold degenerate cases.
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if (Mask.isAllOnesValue())
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return IfSet;
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else if (Mask == 0)
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return IfClr;
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// Transform the DAG into an equivalent VSELECT.
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return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfClr, IfSet);
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}
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return SDValue();
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}
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static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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@ -777,6 +882,9 @@ MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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case ISD::AND:
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Val = performANDCombine(N, DAG, DCI, Subtarget);
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break;
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case ISD::OR:
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Val = performORCombine(N, DAG, DCI, Subtarget);
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break;
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case ISD::SUBE:
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return performSUBECombine(N, DAG, DCI, Subtarget);
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case ISD::MUL:
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@ -972,6 +972,170 @@ define void @ctlz_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
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; CHECK: .size ctlz_v2i64
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}
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define void @bsel_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
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; CHECK: bsel_v16i8:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = and <16 x i8> %1, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6,
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i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
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%4 = and <16 x i8> %2, <i8 249, i8 249, i8 249, i8 249,
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i8 249, i8 249, i8 249, i8 249,
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i8 249, i8 249, i8 249, i8 249,
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i8 249, i8 249, i8 249, i8 249>
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%5 = or <16 x i8> %3, %4
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; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 6
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; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
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store <16 x i8> %5, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size bsel_v16i8
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}
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define void @bsel_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
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; CHECK: bsel_v8i16:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = and <8 x i16> %1, <i16 6, i16 6, i16 6, i16 6,
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i16 6, i16 6, i16 6, i16 6>
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%4 = and <8 x i16> %2, <i16 65529, i16 65529, i16 65529, i16 65529,
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i16 65529, i16 65529, i16 65529, i16 65529>
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%5 = or <8 x i16> %3, %4
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; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 6
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; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
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store <8 x i16> %5, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size bsel_v8i16
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}
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define void @bsel_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
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; CHECK: bsel_v4i32:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = and <4 x i32> %1, <i32 6, i32 6, i32 6, i32 6>
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%4 = and <4 x i32> %2, <i32 4294967289, i32 4294967289, i32 4294967289, i32 4294967289>
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%5 = or <4 x i32> %3, %4
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; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 6
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; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
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store <4 x i32> %5, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size bsel_v4i32
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}
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define void @bsel_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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; CHECK: bsel_v2i64:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = and <2 x i64> %1, <i64 6, i64 6>
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%4 = and <2 x i64> %2, <i64 18446744073709551609, i64 18446744073709551609>
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%5 = or <2 x i64> %3, %4
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; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 6
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; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
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store <2 x i64> %5, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size bsel_v2i64
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}
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define void @binsr_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
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; CHECK: binsr_v16i8_i:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = and <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3,
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i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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%4 = and <16 x i8> %2, <i8 252, i8 252, i8 252, i8 252,
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i8 252, i8 252, i8 252, i8 252,
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i8 252, i8 252, i8 252, i8 252,
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i8 252, i8 252, i8 252, i8 252>
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%5 = or <16 x i8> %3, %4
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; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 3
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; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
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store <16 x i8> %5, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size binsr_v16i8_i
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}
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define void @binsr_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
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; CHECK: binsr_v8i16_i:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = and <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3,
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i16 3, i16 3, i16 3, i16 3>
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%4 = and <8 x i16> %2, <i16 65532, i16 65532, i16 65532, i16 65532,
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i16 65532, i16 65532, i16 65532, i16 65532>
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%5 = or <8 x i16> %3, %4
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; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 3
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; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
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store <8 x i16> %5, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size binsr_v8i16_i
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}
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define void @binsr_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
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; CHECK: binsr_v4i32_i:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
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%4 = and <4 x i32> %2, <i32 4294967292, i32 4294967292, i32 4294967292, i32 4294967292>
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%5 = or <4 x i32> %3, %4
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; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 3
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; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
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store <4 x i32> %5, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size binsr_v4i32_i
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}
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define void @binsr_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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; CHECK: binsr_v2i64_i:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = and <2 x i64> %1, <i64 3, i64 3>
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%4 = and <2 x i64> %2, <i64 18446744073709551612, i64 18446744073709551612>
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%5 = or <2 x i64> %3, %4
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; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 3
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; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
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store <2 x i64> %5, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size binsr_v2i64_i
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}
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declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %val)
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declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %val)
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declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val)
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