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[AArch64] Add ARMv8.2-A new AT instruction variants
ARMv8.2-A adds new variants of the "at" (address translate) system instruction, which take the PSTATE.PAN bit (added in ARMv8.1-A). These are a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15018 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254159 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2513,6 +2513,20 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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} else if (!Op.compare_lower("s12e0w")) {
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} else if (!Op.compare_lower("s12e0w")) {
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// SYS #4, C7, C8, #7
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// SYS #4, C7, C8, #7
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SYS_ALIAS(4, 7, 8, 7);
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SYS_ALIAS(4, 7, 8, 7);
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} else if (!Op.compare_lower("s1e1rp")) {
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if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
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// SYS #0, C7, C9, #0
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SYS_ALIAS(0, 7, 9, 0);
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} else {
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return TokError("AT S1E1RP requires ARMv8.2a");
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}
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} else if (!Op.compare_lower("s1e1wp")) {
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if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
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// SYS #0, C7, C9, #1
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SYS_ALIAS(0, 7, 9, 1);
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} else {
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return TokError("AT S1E1WP requires ARMv8.2a");
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}
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} else {
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} else {
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return TokError("invalid operand for AT instruction");
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return TokError("invalid operand for AT instruction");
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}
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}
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@ -780,6 +780,21 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
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break;
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break;
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}
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}
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break;
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break;
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case 9:
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switch (Op1Val) {
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default:
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break;
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case 0:
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if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
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switch (Op2Val) {
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default:
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break;
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case 0: Asm = "at\ts1e1rp"; break;
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case 1: Asm = "at\ts1e1wp"; break;
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}
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}
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break;
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}
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}
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}
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} else if (CnVal == 8) {
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} else if (CnVal == 8) {
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// TLBI aliases
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// TLBI aliases
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@ -337,7 +337,9 @@ namespace AArch64AT {
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S12E1R = 0x63c4, // 01 100 0111 1000 100
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S12E1R = 0x63c4, // 01 100 0111 1000 100
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S12E1W = 0x63c5, // 01 100 0111 1000 101
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S12E1W = 0x63c5, // 01 100 0111 1000 101
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S12E0R = 0x63c6, // 01 100 0111 1000 110
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S12E0R = 0x63c6, // 01 100 0111 1000 110
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S12E0W = 0x63c7 // 01 100 0111 1000 111
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S12E0W = 0x63c7, // 01 100 0111 1000 111
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S1E1RP = 0x43c8, // 01 000 0111 1001 000
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S1E1WP = 0x43c9 // 01 000 0111 1001 001
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};
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};
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struct ATMapper : AArch64NamedImmMapper {
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struct ATMapper : AArch64NamedImmMapper {
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9
test/MC/AArch64/armv8.2a-at.s
Normal file
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test/MC/AArch64/armv8.2a-at.s
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@ -0,0 +1,9 @@
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
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at s1e1rp, x1
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at s1e1wp, x2
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// CHECK: at s1e1rp, x1 // encoding: [0x01,0x79,0x08,0xd5]
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// CHECK: at s1e1wp, x2 // encoding: [0x22,0x79,0x08,0xd5]
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// ERROR: error: AT S1E1RP requires ARMv8.2a
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// ERROR: error: AT S1E1WP requires ARMv8.2a
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9
test/MC/Disassembler/AArch64/armv8.2a-at.txt
Normal file
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test/MC/Disassembler/AArch64/armv8.2a-at.txt
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@ -0,0 +1,9 @@
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# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a --disassemble < %s | FileCheck %s --check-prefix=NO_V82
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[0x01,0x79,0x08,0xd5]
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[0x22,0x79,0x08,0xd5]
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# CHECK: at s1e1rp, x1
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# CHECK: at s1e1wp, x2
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# NO_V82: sys #0, c7, c9, #0, x1
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# NO_V82: sys #0, c7, c9, #1, x2
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