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[AArch64] Add ARMv8.2-A new AT instruction variants

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ARMv8.2-A adds new variants of the "at" (address translate) system
instruction, which take the PSTATE.PAN bit (added in ARMv8.1-A). These
are a required part of ARMv8.2-A, so no additional subtarget features
are required.

Differential Revision: http://reviews.llvm.org/D15018



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254159 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oliver Stannard 2015-11-26 15:34:44 +00:00
parent 937e2d588c
commit a890b48abb
5 changed files with 50 additions and 1 deletions
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14
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -2513,6 +2513,20 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
} else if (!Op.compare_lower("s12e0w")) { } else if (!Op.compare_lower("s12e0w")) {
// SYS #4, C7, C8, #7 // SYS #4, C7, C8, #7
SYS_ALIAS(4, 7, 8, 7); SYS_ALIAS(4, 7, 8, 7);
} else if (!Op.compare_lower("s1e1rp")) {
if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
// SYS #0, C7, C9, #0
SYS_ALIAS(0, 7, 9, 0);
} else {
return TokError("AT S1E1RP requires ARMv8.2a");
}
} else if (!Op.compare_lower("s1e1wp")) {
if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
// SYS #0, C7, C9, #1
SYS_ALIAS(0, 7, 9, 1);
} else {
return TokError("AT S1E1WP requires ARMv8.2a");
}
} else { } else {
return TokError("invalid operand for AT instruction"); return TokError("invalid operand for AT instruction");
} }

15
lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
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@ -780,6 +780,21 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
break; break;
} }
break; break;
case 9:
switch (Op1Val) {
default:
break;
case 0:
if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
switch (Op2Val) {
default:
break;
case 0: Asm = "at\ts1e1rp"; break;
case 1: Asm = "at\ts1e1wp"; break;
}
}
break;
}
} }
} else if (CnVal == 8) { } else if (CnVal == 8) {
// TLBI aliases // TLBI aliases

4
lib/Target/AArch64/Utils/AArch64BaseInfo.h
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@ -337,7 +337,9 @@ namespace AArch64AT {
S12E1R = 0x63c4, // 01 100 0111 1000 100 S12E1R = 0x63c4, // 01 100 0111 1000 100
S12E1W = 0x63c5, // 01 100 0111 1000 101 S12E1W = 0x63c5, // 01 100 0111 1000 101
S12E0R = 0x63c6, // 01 100 0111 1000 110 S12E0R = 0x63c6, // 01 100 0111 1000 110
S12E0W = 0x63c7 // 01 100 0111 1000 111 S12E0W = 0x63c7, // 01 100 0111 1000 111
S1E1RP = 0x43c8, // 01 000 0111 1001 000
S1E1WP = 0x43c9 // 01 000 0111 1001 001
}; };
struct ATMapper : AArch64NamedImmMapper { struct ATMapper : AArch64NamedImmMapper {

9
test/MC/AArch64/armv8.2a-at.s Normal file
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@ -0,0 +1,9 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
at s1e1rp, x1
at s1e1wp, x2
// CHECK: at s1e1rp, x1 // encoding: [0x01,0x79,0x08,0xd5]
// CHECK: at s1e1wp, x2 // encoding: [0x22,0x79,0x08,0xd5]
// ERROR: error: AT S1E1RP requires ARMv8.2a
// ERROR: error: AT S1E1WP requires ARMv8.2a

9
test/MC/Disassembler/AArch64/armv8.2a-at.txt Normal file
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@ -0,0 +1,9 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a --disassemble < %s | FileCheck %s --check-prefix=NO_V82
[0x01,0x79,0x08,0xd5]
[0x22,0x79,0x08,0xd5]
# CHECK: at s1e1rp, x1
# CHECK: at s1e1wp, x2
# NO_V82: sys #0, c7, c9, #0, x1
# NO_V82: sys #0, c7, c9, #1, x2