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Docs: fix sign of division and increase equivocation on code generated.

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I should have been a politician.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199092 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-01-13 10:47:04 +00:00
parent 54d3aa1537
commit a917400584
1 changed files with 5 additions and 5 deletions
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10
docs/CodeGenerator.rst
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@ -434,12 +434,12 @@ For example, consider this simple LLVM example:
.. code-block:: llvm
define i32 @test(i32 %X, i32 %Y) {
%Z = udiv i32 %X, %Y
%Z = sdiv i32 %X, %Y
ret i32 %Z
}
The X86 instruction selector produces this machine code for the ``div`` and
``ret`` (use "``llc X.bc -march=x86 -print-machineinstrs``" to get this):
The X86 instruction selector might produce this machine code for the ``div`` and
``ret``:
.. code-block:: llvm
@ -454,8 +454,8 @@ The X86 instruction selector produces this machine code for the ``div`` and
%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
ret
By the end of code generation, the register allocator has coalesced the
registers and deleted the resultant identity moves producing the following
By the end of code generation, the register allocator would coalesce the
registers and delete the resultant identity moves producing the following
code:
.. code-block:: llvm