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Check and allow floating point registers to select the size of the

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register for inline asm. This conforms to how gcc allows for effective
casting of inputs into gprs (fprs is already handled).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174008 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2013-01-31 00:50:46 +00:00
parent 946317d07b
commit a9bd4b4647
2 changed files with 44 additions and 2 deletions
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4
lib/Target/X86/X86ISelLowering.cpp
View File

@ -18170,7 +18170,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Res.first = DestReg;
Res.second = &X86::GR8RegClass;
}
} else if (VT == MVT::i32) {
} else if (VT == MVT::i32 || VT == MVT::f32) {
unsigned DestReg = 0;
switch (Res.first) {
default: break;
@ -18187,7 +18187,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Res.first = DestReg;
Res.second = &X86::GR32RegClass;
}
} else if (VT == MVT::i64) {
} else if (VT == MVT::i64 || VT == MVT::f64) {
unsigned DestReg = 0;
switch (Res.first) {
default: break;

42
test/CodeGen/X86/cas.ll Normal file
View File

@ -0,0 +1,42 @@
; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - | FileCheck %s
; C code this came from
;bool cas(float volatile *p, float *expected, float desired) {
; bool success;
; __asm__ __volatile__("lock; cmpxchg %[desired], %[mem]; "
; "mov %[expected], %[expected_out]; "
; "sete %[success]"
; : [success] "=a" (success),
; [expected_out] "=rm" (*expected)
; : [expected] "a" (*expected),
; [desired] "q" (desired),
; [mem] "m" (*p)
; : "memory", "cc");
; return success;
;}
define zeroext i1 @cas(float* %p, float* %expected, float %desired) nounwind {
entry:
%p.addr = alloca float*, align 8
%expected.addr = alloca float*, align 8
%desired.addr = alloca float, align 4
%success = alloca i8, align 1
store float* %p, float** %p.addr, align 8
store float* %expected, float** %expected.addr, align 8
store float %desired, float* %desired.addr, align 4
%0 = load float** %expected.addr, align 8
%1 = load float** %expected.addr, align 8
%2 = load float* %1, align 4
%3 = load float* %desired.addr, align 4
%4 = load float** %p.addr, align 8
%5 = call i8 asm sideeffect "lock; cmpxchg $3, $4; mov $2, $1; sete $0", "={ax},=*rm,{ax},q,*m,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(float* %0, float %2, float %3, float* %4) nounwind
store i8 %5, i8* %success, align 1
%6 = load i8* %success, align 1
%tobool = trunc i8 %6 to i1
ret i1 %tobool
}
; Make sure we're emitting a move from
; CHECK: #APP
; CHECK-NEXT: lock;{{.*}}mov %eax,{{.*}}
; CHECK-NEXT: #NO_APP