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R600/SI: Consistently put soffset before the offset operand for mubuf instructions

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This matches the assembly syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230758 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-02-27 14:59:44 +00:00
parent 4ed3bf29cd
commit a9c15883ba
3 changed files with 20 additions and 20 deletions
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32
lib/Target/R600/SIInstrInfo.td
View File

@ -1861,14 +1861,14 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
defm _ADDR64 : MUBUFAtomicAddr64_m < defm _ADDR64 : MUBUFAtomicAddr64_m <
op, name#"_addr64", (outs), op, name#"_addr64", (outs),
(ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
mbuf_offset:$offset, SCSrc_32:$soffset, slc:$slc), SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
>; >;
defm _OFFSET : MUBUFAtomicOffset_m < defm _OFFSET : MUBUFAtomicOffset_m <
op, name#"_offset", (outs), op, name#"_offset", (outs),
(ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset, (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
SCSrc_32:$soffset, slc:$slc), slc:$slc),
name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
>; >;
} // glc = 0 } // glc = 0
@ -1880,7 +1880,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
defm _RTN_ADDR64 : MUBUFAtomicAddr64_m < defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
op, name#"_rtn_addr64", (outs rc:$vdata), op, name#"_rtn_addr64", (outs rc:$vdata),
(ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr, (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc), SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc", name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
[(set vt:$vdata, [(set vt:$vdata,
(atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
@ -1889,8 +1889,8 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
defm _RTN_OFFSET : MUBUFAtomicOffset_m < defm _RTN_OFFSET : MUBUFAtomicOffset_m <
op, name#"_rtn_offset", (outs rc:$vdata), op, name#"_rtn_offset", (outs rc:$vdata),
(ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset, (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
SCSrc_32:$soffset, slc:$slc), mbuf_offset:$offset, slc:$slc),
name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc", name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
[(set vt:$vdata, [(set vt:$vdata,
(atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
@ -1909,9 +1909,8 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
let mayLoad = 1, mayStore = 0 in { let mayLoad = 1, mayStore = 0 in {
let offen = 0, idxen = 0, vaddr = 0 in { let offen = 0, idxen = 0, vaddr = 0 in {
defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata), defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
(ins SReg_128:$srsrc, (ins SReg_128:$srsrc, SCSrc_32:$soffset,
mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
slc:$slc, tfe:$tfe),
name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
[(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc, [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
i32:$soffset, i16:$offset, i32:$soffset, i16:$offset,
@ -1929,15 +1928,15 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
let offen = 0, idxen = 1 in { let offen = 0, idxen = 1 in {
defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata), defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
(ins SReg_128:$srsrc, VGPR_32:$vaddr, (ins SReg_128:$srsrc, VGPR_32:$vaddr,
mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc, SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
slc:$slc, tfe:$tfe), slc:$slc, tfe:$tfe),
name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
} }
let offen = 1, idxen = 1 in { let offen = 1, idxen = 1 in {
defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata), defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
(ins SReg_128:$srsrc, VReg_64:$vaddr, (ins SReg_128:$srsrc, VReg_64:$vaddr, SCSrc_32:$soffset,
SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
} }
@ -1968,8 +1967,8 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
let offen = 0, idxen = 0, vaddr = 0 in { let offen = 0, idxen = 0, vaddr = 0 in {
defm _OFFSET : MUBUF_m <op, name#"_offset",(outs), defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
(ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset, (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe), mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
[(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>; i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
@ -1977,8 +1976,9 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
let offen = 1, idxen = 0 in { let offen = 1, idxen = 0 in {
defm _OFFEN : MUBUF_m <op, name#"_offen", (outs), defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
(ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset, (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr,
mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
slc:$slc, tfe:$tfe),
name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"# name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
"$glc"#"$slc"#"$tfe", []>; "$glc"#"$slc"#"$tfe", []>;
} // end offen = 1, idxen = 0 } // end offen = 1, idxen = 0

6
lib/Target/R600/SIInstructions.td
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@ -2049,7 +2049,7 @@ def : Pat <
/* int_SI_vs_load_input */ /* int_SI_vs_load_input */
def : Pat< def : Pat<
(SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr), (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
(BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0) (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, 0, imm:$attr_offset, 0, 0, 0)
>; >;
/* int_SI_export */ /* int_SI_export */
@ -2936,7 +2936,7 @@ multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxe
(vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset, (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
imm:$offset, 0, 0, imm:$glc, imm:$slc, imm:$offset, 0, 0, imm:$glc, imm:$slc,
imm:$tfe)), imm:$tfe)),
(offset $rsrc, (as_i16imm $offset), $soffset, (as_i1imm $glc), (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
(as_i1imm $slc), (as_i1imm $tfe)) (as_i1imm $slc), (as_i1imm $tfe))
>; >;
@ -2952,7 +2952,7 @@ multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxe
(vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
imm:$offset, 0, 1, imm:$glc, imm:$slc, imm:$offset, 0, 1, imm:$glc, imm:$slc,
imm:$tfe)), imm:$tfe)),
(idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), (idxen $rsrc, $vaddr, $soffset, (as_i16imm $offset), (as_i1imm $glc),
(as_i1imm $slc), (as_i1imm $tfe)) (as_i1imm $slc), (as_i1imm $tfe))
>; >;

2
lib/Target/R600/SIRegisterInfo.cpp
View File

@ -162,8 +162,8 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp)) BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
.addReg(SubReg, getDefRegState(IsLoad)) .addReg(SubReg, getDefRegState(IsLoad))
.addReg(ScratchRsrcReg, getKillRegState(IsKill)) .addReg(ScratchRsrcReg, getKillRegState(IsKill))
.addImm(Offset)
.addReg(SOffset) .addReg(SOffset)
.addImm(Offset)
.addImm(0) // glc .addImm(0) // glc
.addImm(0) // slc .addImm(0) // slc
.addImm(0) // tfe .addImm(0) // tfe