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R600/SI: Fix f64 inline immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224458 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
648facfff4
commit
aa14ffddcf
@ -70,9 +70,14 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_FPImmediate: {
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const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
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assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle &&
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"Only floating point immediates are supported at the moment.");
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MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
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if (&FloatValue.getSemantics() == &APFloat::IEEEsingle)
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MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
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else if (&FloatValue.getSemantics() == &APFloat::IEEEdouble)
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MCOp = MCOperand::CreateFPImm(FloatValue.convertToDouble());
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else
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llvm_unreachable("Unhandled floating point type");
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break;
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}
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case MachineOperand::MO_Immediate:
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@ -14,6 +14,7 @@
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/MathExtras.h"
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@ -208,7 +209,7 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
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O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
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}
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void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
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void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
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int32_t SImm = static_cast<int32_t>(Imm);
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if (SImm >= -16 && SImm <= 64) {
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O << SImm;
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@ -233,9 +234,37 @@ void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
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O << "4.0";
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else if (Imm == FloatToBits(-4.0f))
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O << "-4.0";
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else {
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else
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O << formatHex(static_cast<uint64_t>(Imm));
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}
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void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
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int64_t SImm = static_cast<int64_t>(Imm);
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if (SImm >= -16 && SImm <= 64) {
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O << SImm;
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return;
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}
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if (Imm == DoubleToBits(0.0))
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O << "0.0";
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else if (Imm == DoubleToBits(1.0))
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O << "1.0";
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else if (Imm == DoubleToBits(-1.0))
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O << "-1.0";
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else if (Imm == DoubleToBits(0.5))
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O << "0.5";
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else if (Imm == DoubleToBits(-0.5))
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O << "-0.5";
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else if (Imm == DoubleToBits(2.0))
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O << "2.0";
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else if (Imm == DoubleToBits(-2.0))
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O << "-2.0";
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else if (Imm == DoubleToBits(4.0))
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O << "4.0";
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else if (Imm == DoubleToBits(-4.0))
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O << "-4.0";
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else
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llvm_unreachable("64-bit literal constants not supported");
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}
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void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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@ -253,14 +282,37 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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break;
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}
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} else if (Op.isImm()) {
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printImmediate(Op.getImm(), O);
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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int RCID = Desc.OpInfo[OpNo].RegClass;
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if (RCID != -1) {
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const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
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if (ImmRC.getSize() == 4)
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printImmediate32(Op.getImm(), O);
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else if (ImmRC.getSize() == 8)
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printImmediate64(Op.getImm(), O);
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else
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llvm_unreachable("Invalid register class size");
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} else {
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// We hit this for the immediate instruction bits that don't yet have a
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// custom printer.
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// TODO: Eventually this should be unnecessary.
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O << formatDec(Op.getImm());
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}
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} else if (Op.isFPImm()) {
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// We special case 0.0 because otherwise it will be printed as an integer.
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if (Op.getFPImm() == 0.0)
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O << "0.0";
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else
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printImmediate(FloatToBits(Op.getFPImm()), O);
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else {
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
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if (ImmRC.getSize() == 4)
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printImmediate32(FloatToBits(Op.getFPImm()), O);
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else if (ImmRC.getSize() == 8)
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printImmediate64(DoubleToBits(Op.getFPImm()), O);
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else
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llvm_unreachable("Invalid register class size");
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}
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} else if (Op.isExpr()) {
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const MCExpr *Exp = Op.getExpr();
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Exp->print(O);
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@ -48,7 +48,8 @@ private:
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void printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printTFE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printRegOperand(unsigned RegNo, raw_ostream &O);
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void printImmediate(uint32_t Imm, raw_ostream &O);
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void printImmediate32(uint32_t I, raw_ostream &O);
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void printImmediate64(uint64_t I, raw_ostream &O);
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printOperandAndMods(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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@ -1578,31 +1578,30 @@ static bool isSSrc(unsigned RegClass) {
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/// and the immediate value if it's a literal immediate
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int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
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union {
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int32_t I;
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float F;
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} Imm;
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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getTargetMachine().getSubtargetImpl()->getInstrInfo());
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if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
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if (Node->getZExtValue() >> 32) {
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return -1;
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}
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Imm.I = Node->getSExtValue();
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} else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
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if (N->getValueType(0) != MVT::f32)
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if (Node->getZExtValue() >> 32)
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return -1;
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Imm.F = Node->getValueAPF().convertToFloat();
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} else
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return -1; // It isn't an immediate
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if ((Imm.I >= -16 && Imm.I <= 64) ||
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Imm.F == 0.5f || Imm.F == -0.5f ||
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Imm.F == 1.0f || Imm.F == -1.0f ||
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Imm.F == 2.0f || Imm.F == -2.0f ||
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Imm.F == 4.0f || Imm.F == -4.0f)
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return 0; // It's an inline immediate
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if (TII->isInlineConstant(Node->getAPIntValue()))
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return 0;
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return Imm.I; // It's a literal immediate
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return Node->getZExtValue();
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}
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if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
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if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
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return 0;
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if (Node->getValueType(0) == MVT::f32)
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return FloatToBits(Node->getValueAPF().convertToFloat());
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return -1;
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}
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return -1;
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}
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/// \brief Try to fold an immediate directly into an instruction
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@ -896,10 +896,23 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
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}
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bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
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int32_t Val = Imm.getSExtValue();
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if (Val >= -16 && Val <= 64)
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int64_t SVal = Imm.getSExtValue();
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if (SVal >= -16 && SVal <= 64)
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return true;
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if (Imm.getBitWidth() == 64) {
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uint64_t Val = Imm.getZExtValue();
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return (DoubleToBits(0.0) == Val) ||
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(DoubleToBits(1.0) == Val) ||
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(DoubleToBits(-1.0) == Val) ||
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(DoubleToBits(0.5) == Val) ||
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(DoubleToBits(-0.5) == Val) ||
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(DoubleToBits(2.0) == Val) ||
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(DoubleToBits(-2.0) == Val) ||
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(DoubleToBits(4.0) == Val) ||
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(DoubleToBits(-4.0) == Val);
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}
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// The actual type of the operand does not seem to matter as long
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// as the bits match one of the inline immediate values. For example:
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//
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@ -908,16 +921,17 @@ bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
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//
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// 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
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// floating-point, so it is a legal inline immediate.
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uint32_t Val = Imm.getZExtValue();
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return (APInt::floatToBits(0.0f) == Imm) ||
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(APInt::floatToBits(1.0f) == Imm) ||
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(APInt::floatToBits(-1.0f) == Imm) ||
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(APInt::floatToBits(0.5f) == Imm) ||
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(APInt::floatToBits(-0.5f) == Imm) ||
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(APInt::floatToBits(2.0f) == Imm) ||
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(APInt::floatToBits(-2.0f) == Imm) ||
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(APInt::floatToBits(4.0f) == Imm) ||
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(APInt::floatToBits(-4.0f) == Imm);
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return (FloatToBits(0.0f) == Val) ||
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(FloatToBits(1.0f) == Val) ||
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(FloatToBits(-1.0f) == Val) ||
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(FloatToBits(0.5f) == Val) ||
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(FloatToBits(-0.5f) == Val) ||
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(FloatToBits(2.0f) == Val) ||
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(FloatToBits(-2.0f) == Val) ||
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(FloatToBits(4.0f) == Val) ||
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(FloatToBits(-4.0f) == Val);
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}
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bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
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@ -188,6 +188,10 @@ class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
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return isInlineImmediate(N);
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}]>;
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class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
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return isInlineImmediate(N);
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}]>;
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class SGPRImm <dag frag> : PatLeaf<frag, [{
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if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
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AMDGPUSubtarget::SOUTHERN_ISLANDS) {
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@ -2572,6 +2572,11 @@ def : Pat <
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(S_MOV_B64 (i64 (as_i64imm $imm)))
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>;
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def : Pat <
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(f64 InlineFPImm<f64>:$imm),
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(S_MOV_B64 InlineFPImm<f64>:$imm)
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>;
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/********** ===================== **********/
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/********** Interpolation Paterns **********/
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/********** ===================== **********/
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@ -184,9 +184,9 @@ def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
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(add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
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>;
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def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;
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def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 64, (add SGPR_64Regs)>;
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def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
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def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 64,
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(add SGPR_64, VCCReg, EXECReg, FLAT_SCR)
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>;
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@ -30,6 +30,14 @@ define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
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ret void
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}
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; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32
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; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
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store float -0.0, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32
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; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
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; CHECK-NEXT: buffer_store_dword [[REG]]
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@ -213,3 +221,267 @@ define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_1_f32
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; CHECK: s_load_dword [[VAL:s[0-9]+]]
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; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
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%y = fadd float %x, 0x36a0000000000000
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_2_f32
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; CHECK: s_load_dword [[VAL:s[0-9]+]]
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; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
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%y = fadd float %x, 0x36b0000000000000
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_16_f32
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; CHECK: s_load_dword [[VAL:s[0-9]+]]
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; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]]
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
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%y = fadd float %x, 0x36e0000000000000
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32
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; CHECK: s_load_dword [[VAL:s[0-9]+]]
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; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]]
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
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%y = fadd float %x, 0xffffffffe0000000
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32
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; CHECK: s_load_dword [[VAL:s[0-9]+]]
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; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]]
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) {
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%y = fadd float %x, 0xffffffffc0000000
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32
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; CHECK: s_load_dword [[VAL:s[0-9]+]]
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; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]]
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) {
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%y = fadd float %x, 0xfffffffe00000000
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_63_f32
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; CHECK: s_load_dword [[VAL:s[0-9]+]]
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; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]]
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
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%y = fadd float %x, 0x36ff800000000000
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_64_f32
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; CHECK: s_load_dword [[VAL:s[0-9]+]]
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; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]]
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; CHECK-NEXT: buffer_store_dword [[REG]]
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define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) {
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%y = fadd float %x, 0x3700000000000000
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store float %y, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64
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; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.0, [[VAL]]
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; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
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define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) {
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%y = fadd double %x, 0.0
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store double %y, double addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64
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; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0.5
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, -0.5
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 1.0
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, -1.0
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 2.0
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, -2.0
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 4.0
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, -4.0
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_1_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0x0000000000000001
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_2_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0x0000000000000002
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_16_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0x0000000000000010
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0xffffffffffffffff
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0xfffffffffffffffe
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0xfffffffffffffff0
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_63_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0x000000000000003F
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}add_inline_imm_64_f64
|
||||
; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]]
|
||||
; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
|
||||
define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) {
|
||||
%y = fadd double %x, 0x0000000000000040
|
||||
store double %y, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; FIXME: These shoudn't bother materializing in SGPRs
|
||||
|
||||
; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64
|
||||
; CHECK: s_mov_b64 s{{\[}}[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]{{\]}}, 0{{$}}
|
||||
; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
|
||||
; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
|
||||
; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
|
||||
define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) {
|
||||
store double 0.0, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user