From aad753bbbd98c952f7e65246af2faf5c7d5a850b Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Mon, 10 May 2010 19:03:57 +0000
Subject: [PATCH] Be careful with operand promotion. For a binary operation,
 the source operands may be the same. PR7018. rdar://7939869.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103419 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp      | 14 ++++++++++----
 test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll | 11 +++++++++++
 2 files changed, 21 insertions(+), 4 deletions(-)
 create mode 100644 test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3639f804746..c8d3e0df8d6 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -760,12 +760,18 @@ SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
 
     bool Replace1 = false;
     SDValue N1 = Op.getOperand(1);
-    SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
-    if (NN1.getNode() == 0)
-      return SDValue();
+    SDValue NN1;
+    if (N0 == N1)
+      NN1 = NN0;
+    else {
+      NN1 = PromoteOperand(N1, PVT, Replace1);
+      if (NN1.getNode() == 0)
+        return SDValue();
+    }
 
     AddToWorkList(NN0.getNode());
-    AddToWorkList(NN1.getNode());
+    if (NN1.getNode())
+      AddToWorkList(NN1.getNode());
 
     if (Replace0)
       ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
diff --git a/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll b/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll
new file mode 100644
index 00000000000..e719da304c5
--- /dev/null
+++ b/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10
+; PR7018
+; rdar://7939869
+
+define i32 @CXB30130(i32 %num1, i16* nocapture %num2, float* nocapture %num3, double* nocapture %num4) nounwind ssp {
+entry:
+  %0 = load i16* %num2, align 2                   ; <i16> [#uses=2]
+  %1 = mul nsw i16 %0, %0                         ; <i16> [#uses=1]
+  store i16 %1, i16* %num2, align 2
+  ret i32 undef
+}