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rename indbr -> indirectbr to appease the residents of #llvm.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-10-28 00:19:10 +00:00
parent 2ee11eccdd
commit ab21db79ef
21 changed files with 93 additions and 91 deletions
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16
docs/LangRef.html
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@ -111,7 +111,7 @@
<li><a href="#i_ret">'<tt>ret</tt>' Instruction</a></li> <li><a href="#i_ret">'<tt>ret</tt>' Instruction</a></li>
<li><a href="#i_br">'<tt>br</tt>' Instruction</a></li> <li><a href="#i_br">'<tt>br</tt>' Instruction</a></li>
<li><a href="#i_switch">'<tt>switch</tt>' Instruction</a></li> <li><a href="#i_switch">'<tt>switch</tt>' Instruction</a></li>
<li><a href="#i_indbr">'<tt>indbr</tt>' Instruction</a></li> <li><a href="#i_indirectbr">'<tt>indirectbr</tt>' Instruction</a></li>
<li><a href="#i_invoke">'<tt>invoke</tt>' Instruction</a></li> <li><a href="#i_invoke">'<tt>invoke</tt>' Instruction</a></li>
<li><a href="#i_unwind">'<tt>unwind</tt>' Instruction</a></li> <li><a href="#i_unwind">'<tt>unwind</tt>' Instruction</a></li>
<li><a href="#i_unreachable">'<tt>unreachable</tt>' Instruction</a></li> <li><a href="#i_unreachable">'<tt>unreachable</tt>' Instruction</a></li>
@ -2183,13 +2183,13 @@ has undefined behavior.</p>
the address of the entry block is illegal.</p> the address of the entry block is illegal.</p>
<p>This value only has defined behavior when used as an operand to the <p>This value only has defined behavior when used as an operand to the
'<a href="#i_indbr"><tt>indbr</tt></a>' instruction or for comparisons '<a href="#i_indirectbr"><tt>indirectbr</tt></a>' instruction or for comparisons
against null. Pointer equality tests between labels addresses is undefined against null. Pointer equality tests between labels addresses is undefined
behavior - though, again, comparison against null is ok, and no label is behavior - though, again, comparison against null is ok, and no label is
equal to the null pointer. This may also be passed around as an opaque equal to the null pointer. This may also be passed around as an opaque
pointer sized value as long as the bits are not inspected. This allows pointer sized value as long as the bits are not inspected. This allows
<tt>ptrtoint</tt> and arithmetic to be performed on these values so long as <tt>ptrtoint</tt> and arithmetic to be performed on these values so long as
the original value is reconstituted before the <tt>indbr</tt>.</p> the original value is reconstituted before the <tt>indirectbr</tt>.</p>
<p>Finally, some targets may provide defined semantics when <p>Finally, some targets may provide defined semantics when
using the value as the operand to an inline assembly, but that is target using the value as the operand to an inline assembly, but that is target
@ -2541,7 +2541,7 @@ Instructions</a> </div>
'<a href="#i_ret"><tt>ret</tt></a>' instruction, the '<a href="#i_ret"><tt>ret</tt></a>' instruction, the
'<a href="#i_br"><tt>br</tt></a>' instruction, the '<a href="#i_br"><tt>br</tt></a>' instruction, the
'<a href="#i_switch"><tt>switch</tt></a>' instruction, the '<a href="#i_switch"><tt>switch</tt></a>' instruction, the
'<a href="#i_indbr">'<tt>indbr</tt>' Instruction, the '<a href="#i_indirectbr">'<tt>indirectbr</tt>' Instruction, the
'<a href="#i_invoke"><tt>invoke</tt></a>' instruction, the '<a href="#i_invoke"><tt>invoke</tt></a>' instruction, the
'<a href="#i_unwind"><tt>unwind</tt></a>' instruction, and the '<a href="#i_unwind"><tt>unwind</tt></a>' instruction, and the
'<a href="#i_unreachable"><tt>unreachable</tt></a>' instruction.</p> '<a href="#i_unreachable"><tt>unreachable</tt></a>' instruction.</p>
@ -2703,19 +2703,19 @@ IfUnequal:
<!-- _______________________________________________________________________ --> <!-- _______________________________________________________________________ -->
<div class="doc_subsubsection"> <div class="doc_subsubsection">
<a name="i_indbr">'<tt>indbr</tt>' Instruction</a> <a name="i_indirectbr">'<tt>indirectbr</tt>' Instruction</a>
</div> </div>
<div class="doc_text"> <div class="doc_text">
<h5>Syntax:</h5> <h5>Syntax:</h5>
<pre> <pre>
indbr &lt;somety&gt;* &lt;address&gt;, [ label &lt;dest1&gt;, label &lt;dest2&gt;, ... ] indirectbr &lt;somety&gt;* &lt;address&gt;, [ label &lt;dest1&gt;, label &lt;dest2&gt;, ... ]
</pre> </pre>
<h5>Overview:</h5> <h5>Overview:</h5>
<p>The '<tt>indbr</tt>' instruction implements an indirect branch to a label <p>The '<tt>indirectbr</tt>' instruction implements an indirect branch to a label
within the current function, whose address is specified by within the current function, whose address is specified by
"<tt>address</tt>". Address must be derived from a <a "<tt>address</tt>". Address must be derived from a <a
href="#blockaddress">blockaddress</a> constant.</p> href="#blockaddress">blockaddress</a> constant.</p>
@ -2743,7 +2743,7 @@ IfUnequal:
<h5>Example:</h5> <h5>Example:</h5>
<pre> <pre>
indbr i8* %Addr, [ label %bb1, label %bb2, label %bb3 ] indirectbr i8* %Addr, [ label %bb1, label %bb2, label %bb3 ]
</pre> </pre>
</div> </div>

2
include/llvm/Bitcode/LLVMBitCodes.h
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@ -237,7 +237,7 @@ namespace bitc {
// new select on i1 or [N x i1] // new select on i1 or [N x i1]
FUNC_CODE_INST_VSELECT = 29, // VSELECT: [ty,opval,opval,predty,pred] FUNC_CODE_INST_VSELECT = 29, // VSELECT: [ty,opval,opval,predty,pred]
FUNC_CODE_INST_INBOUNDS_GEP= 30, // INBOUNDS_GEP: [n x operands] FUNC_CODE_INST_INBOUNDS_GEP= 30, // INBOUNDS_GEP: [n x operands]
FUNC_CODE_INST_INDBR = 31 // INDBR: [opty, op0, op1, ...] FUNC_CODE_INST_INDIRECTBR = 31 // INDIRECTBR: [opty, op0, op1, ...]
}; };
} // End bitc namespace } // End bitc namespace
} // End llvm namespace } // End llvm namespace

2
include/llvm/Instruction.def
View File

@ -97,7 +97,7 @@
HANDLE_TERM_INST ( 1, Ret , ReturnInst) HANDLE_TERM_INST ( 1, Ret , ReturnInst)
HANDLE_TERM_INST ( 2, Br , BranchInst) HANDLE_TERM_INST ( 2, Br , BranchInst)
HANDLE_TERM_INST ( 3, Switch , SwitchInst) HANDLE_TERM_INST ( 3, Switch , SwitchInst)
HANDLE_TERM_INST ( 4, IndBr , IndBrInst) HANDLE_TERM_INST ( 4, IndirectBr , IndirectBrInst)
HANDLE_TERM_INST ( 5, Invoke , InvokeInst) HANDLE_TERM_INST ( 5, Invoke , InvokeInst)
HANDLE_TERM_INST ( 6, Unwind , UnwindInst) HANDLE_TERM_INST ( 6, Unwind , UnwindInst)
HANDLE_TERM_INST ( 7, Unreachable, UnreachableInst) HANDLE_TERM_INST ( 7, Unreachable, UnreachableInst)

56
include/llvm/Instructions.h
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@ -2220,61 +2220,61 @@ DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SwitchInst, Value)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// IndBrInst Class // IndirectBrInst Class
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===--------------------------------------------------------------------------- //===---------------------------------------------------------------------------
/// IndBrInst - Indirect Branch Instruction. /// IndirectBrInst - Indirect Branch Instruction.
/// ///
class IndBrInst : public TerminatorInst { class IndirectBrInst : public TerminatorInst {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned); // DO NOT IMPLEMENT
unsigned ReservedSpace; unsigned ReservedSpace;
// Operand[0] = Value to switch on // Operand[0] = Value to switch on
// Operand[1] = Default basic block destination // Operand[1] = Default basic block destination
// Operand[2n ] = Value to match // Operand[2n ] = Value to match
// Operand[2n+1] = BasicBlock to go to on match // Operand[2n+1] = BasicBlock to go to on match
IndBrInst(const IndBrInst &IBI); IndirectBrInst(const IndirectBrInst &IBI);
void init(Value *Address, unsigned NumDests); void init(Value *Address, unsigned NumDests);
void resizeOperands(unsigned No); void resizeOperands(unsigned No);
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
/// IndBrInst ctor - Create a new indbr instruction, specifying an Address to /// IndirectBrInst ctor - Create a new indirectbr instruction, specifying an
/// jump to. The number of expected destinations can be specified here to /// Address to jump to. The number of expected destinations can be specified
/// make memory allocation more efficient. This constructor can also /// here to make memory allocation more efficient. This constructor can also
/// autoinsert before another instruction. /// autoinsert before another instruction.
IndBrInst(Value *Address, unsigned NumDests, Instruction *InsertBefore); IndirectBrInst(Value *Address, unsigned NumDests, Instruction *InsertBefore);
/// IndBrInst ctor - Create a new indbr instruction, specifying an Address to /// IndirectBrInst ctor - Create a new indirectbr instruction, specifying an
/// jump to. The number of expected destinations can be specified here to /// Address to jump to. The number of expected destinations can be specified
/// make memory allocation more efficient. This constructor also autoinserts /// here to make memory allocation more efficient. This constructor also
/// at the end of the specified BasicBlock. /// autoinserts at the end of the specified BasicBlock.
IndBrInst(Value *Address, unsigned NumDests, BasicBlock *InsertAtEnd); IndirectBrInst(Value *Address, unsigned NumDests, BasicBlock *InsertAtEnd);
protected: protected:
virtual IndBrInst *clone_impl() const; virtual IndirectBrInst *clone_impl() const;
public: public:
static IndBrInst *Create(Value *Address, unsigned NumDests, static IndirectBrInst *Create(Value *Address, unsigned NumDests,
Instruction *InsertBefore = 0) { Instruction *InsertBefore = 0) {
return new IndBrInst(Address, NumDests, InsertBefore); return new IndirectBrInst(Address, NumDests, InsertBefore);
} }
static IndBrInst *Create(Value *Address, unsigned NumDests, static IndirectBrInst *Create(Value *Address, unsigned NumDests,
BasicBlock *InsertAtEnd) { BasicBlock *InsertAtEnd) {
return new IndBrInst(Address, NumDests, InsertAtEnd); return new IndirectBrInst(Address, NumDests, InsertAtEnd);
} }
~IndBrInst(); ~IndirectBrInst();
/// Provide fast operand accessors. /// Provide fast operand accessors.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
// Accessor Methods for IndBr instruction. // Accessor Methods for IndirectBrInst instruction.
Value *getAddress() { return getOperand(0); } Value *getAddress() { return getOperand(0); }
const Value *getAddress() const { return getOperand(0); } const Value *getAddress() const { return getOperand(0); }
void setAddress(Value *V) { setOperand(0, V); } void setAddress(Value *V) { setOperand(0, V); }
/// getNumDestinations - return the number of possible destinations in this /// getNumDestinations - return the number of possible destinations in this
/// indbr instruction. /// indirectbr instruction.
unsigned getNumDestinations() const { return getNumOperands()-1; } unsigned getNumDestinations() const { return getNumOperands()-1; }
/// getDestination - Return the specified destination. /// getDestination - Return the specified destination.
@ -2286,7 +2286,7 @@ public:
void addDestination(BasicBlock *Dest); void addDestination(BasicBlock *Dest);
/// removeDestination - This method removes the specified successor from the /// removeDestination - This method removes the specified successor from the
/// indbr instruction. /// indirectbr instruction.
void removeDestination(unsigned i); void removeDestination(unsigned i);
unsigned getNumSuccessors() const { return getNumOperands()-1; } unsigned getNumSuccessors() const { return getNumOperands()-1; }
@ -2298,9 +2298,9 @@ public:
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const IndBrInst *) { return true; } static inline bool classof(const IndirectBrInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::IndBr; return I->getOpcode() == Instruction::IndirectBr;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
@ -2312,10 +2312,10 @@ private:
}; };
template <> template <>
struct OperandTraits<IndBrInst> : public HungoffOperandTraits<1> { struct OperandTraits<IndirectBrInst> : public HungoffOperandTraits<1> {
}; };
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(IndBrInst, Value) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(IndirectBrInst, Value)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

2
include/llvm/Support/InstVisitor.h
View File

@ -160,7 +160,7 @@ public:
RetTy visitReturnInst(ReturnInst &I) { DELEGATE(TerminatorInst);} RetTy visitReturnInst(ReturnInst &I) { DELEGATE(TerminatorInst);}
RetTy visitBranchInst(BranchInst &I) { DELEGATE(TerminatorInst);} RetTy visitBranchInst(BranchInst &I) { DELEGATE(TerminatorInst);}
RetTy visitSwitchInst(SwitchInst &I) { DELEGATE(TerminatorInst);} RetTy visitSwitchInst(SwitchInst &I) { DELEGATE(TerminatorInst);}
RetTy visitIndBrInst(IndBrInst &I) { DELEGATE(TerminatorInst);} RetTy visitIndirectBrInst(IndirectBrInst &I) { DELEGATE(TerminatorInst);}
RetTy visitInvokeInst(InvokeInst &I) { DELEGATE(TerminatorInst);} RetTy visitInvokeInst(InvokeInst &I) { DELEGATE(TerminatorInst);}
RetTy visitUnwindInst(UnwindInst &I) { DELEGATE(TerminatorInst);} RetTy visitUnwindInst(UnwindInst &I) { DELEGATE(TerminatorInst);}
RetTy visitUnreachableInst(UnreachableInst &I) { DELEGATE(TerminatorInst);} RetTy visitUnreachableInst(UnreachableInst &I) { DELEGATE(TerminatorInst);}

2
lib/Analysis/InlineCost.cpp
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@ -31,7 +31,7 @@ unsigned InlineCostAnalyzer::FunctionInfo::
// Eliminating a switch is a big win, proportional to the number of edges // Eliminating a switch is a big win, proportional to the number of edges
// deleted. // deleted.
Reduction += (SI->getNumSuccessors()-1) * 40; Reduction += (SI->getNumSuccessors()-1) * 40;
else if (isa<IndBrInst>(*UI)) else if (isa<IndirectBrInst>(*UI))
// Eliminating an indirect branch is a big win. // Eliminating an indirect branch is a big win.
Reduction += 200; Reduction += 200;
else if (CallInst *CI = dyn_cast<CallInst>(*UI)) { else if (CallInst *CI = dyn_cast<CallInst>(*UI)) {

2
lib/Analysis/SparsePropagation.cpp
View File

@ -166,7 +166,7 @@ void SparseSolver::getFeasibleSuccessors(TerminatorInst &TI,
return; return;
} }
if (isa<IndBrInst>(TI)) { if (isa<IndirectBrInst>(TI)) {
Succs.assign(Succs.size(), true); Succs.assign(Succs.size(), true);
return; return;
} }

2
lib/AsmParser/LLLexer.cpp
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@ -645,7 +645,7 @@ lltok::Kind LLLexer::LexIdentifier() {
INSTKEYWORD(ret, Ret); INSTKEYWORD(ret, Ret);
INSTKEYWORD(br, Br); INSTKEYWORD(br, Br);
INSTKEYWORD(switch, Switch); INSTKEYWORD(switch, Switch);
INSTKEYWORD(indbr, IndBr); INSTKEYWORD(indirectbr, IndirectBr);
INSTKEYWORD(invoke, Invoke); INSTKEYWORD(invoke, Invoke);
INSTKEYWORD(unwind, Unwind); INSTKEYWORD(unwind, Unwind);
INSTKEYWORD(unreachable, Unreachable); INSTKEYWORD(unreachable, Unreachable);

16
lib/AsmParser/LLParser.cpp
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@ -2731,7 +2731,7 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
case lltok::kw_ret: return ParseRet(Inst, BB, PFS); case lltok::kw_ret: return ParseRet(Inst, BB, PFS);
case lltok::kw_br: return ParseBr(Inst, PFS); case lltok::kw_br: return ParseBr(Inst, PFS);
case lltok::kw_switch: return ParseSwitch(Inst, PFS); case lltok::kw_switch: return ParseSwitch(Inst, PFS);
case lltok::kw_indbr: return ParseIndBr(Inst, PFS); case lltok::kw_indirectbr: return ParseIndirectBr(Inst, PFS);
case lltok::kw_invoke: return ParseInvoke(Inst, PFS); case lltok::kw_invoke: return ParseInvoke(Inst, PFS);
// Binary Operators. // Binary Operators.
case lltok::kw_add: case lltok::kw_add:
@ -3004,19 +3004,19 @@ bool LLParser::ParseSwitch(Instruction *&Inst, PerFunctionState &PFS) {
return false; return false;
} }
/// ParseIndBr /// ParseIndirectBr
/// Instruction /// Instruction
/// ::= 'indbr' TypeAndValue ',' '[' LabelList ']' /// ::= 'indirectbr' TypeAndValue ',' '[' LabelList ']'
bool LLParser::ParseIndBr(Instruction *&Inst, PerFunctionState &PFS) { bool LLParser::ParseIndirectBr(Instruction *&Inst, PerFunctionState &PFS) {
LocTy AddrLoc; LocTy AddrLoc;
Value *Address; Value *Address;
if (ParseTypeAndValue(Address, AddrLoc, PFS) || if (ParseTypeAndValue(Address, AddrLoc, PFS) ||
ParseToken(lltok::comma, "expected ',' after indbr address") || ParseToken(lltok::comma, "expected ',' after indirectbr address") ||
ParseToken(lltok::lsquare, "expected '[' with indbr")) ParseToken(lltok::lsquare, "expected '[' with indirectbr"))
return true; return true;
if (!isa<PointerType>(Address->getType())) if (!isa<PointerType>(Address->getType()))
return Error(AddrLoc, "indbr address must have pointer type"); return Error(AddrLoc, "indirectbr address must have pointer type");
// Parse the destination list. // Parse the destination list.
SmallVector<BasicBlock*, 16> DestList; SmallVector<BasicBlock*, 16> DestList;
@ -3037,7 +3037,7 @@ bool LLParser::ParseIndBr(Instruction *&Inst, PerFunctionState &PFS) {
if (ParseToken(lltok::rsquare, "expected ']' at end of block list")) if (ParseToken(lltok::rsquare, "expected ']' at end of block list"))
return true; return true;
IndBrInst *IBI = IndBrInst::Create(Address, DestList.size()); IndirectBrInst *IBI = IndirectBrInst::Create(Address, DestList.size());
for (unsigned i = 0, e = DestList.size(); i != e; ++i) for (unsigned i = 0, e = DestList.size(); i != e; ++i)
IBI->addDestination(DestList[i]); IBI->addDestination(DestList[i]);
Inst = IBI; Inst = IBI;

2
lib/AsmParser/LLParser.h
View File

@ -270,7 +270,7 @@ namespace llvm {
bool ParseRet(Instruction *&Inst, BasicBlock *BB, PerFunctionState &PFS); bool ParseRet(Instruction *&Inst, BasicBlock *BB, PerFunctionState &PFS);
bool ParseBr(Instruction *&Inst, PerFunctionState &PFS); bool ParseBr(Instruction *&Inst, PerFunctionState &PFS);
bool ParseSwitch(Instruction *&Inst, PerFunctionState &PFS); bool ParseSwitch(Instruction *&Inst, PerFunctionState &PFS);
bool ParseIndBr(Instruction *&Inst, PerFunctionState &PFS); bool ParseIndirectBr(Instruction *&Inst, PerFunctionState &PFS);
bool ParseInvoke(Instruction *&Inst, PerFunctionState &PFS); bool ParseInvoke(Instruction *&Inst, PerFunctionState &PFS);
bool ParseArithmetic(Instruction *&I, PerFunctionState &PFS, unsigned Opc, bool ParseArithmetic(Instruction *&I, PerFunctionState &PFS, unsigned Opc,

3
lib/AsmParser/LLToken.h
View File

@ -111,7 +111,8 @@ namespace lltok {
kw_fptoui, kw_fptosi, kw_inttoptr, kw_ptrtoint, kw_bitcast, kw_fptoui, kw_fptosi, kw_inttoptr, kw_ptrtoint, kw_bitcast,
kw_select, kw_va_arg, kw_select, kw_va_arg,
kw_ret, kw_br, kw_switch, kw_indbr, kw_invoke, kw_unwind, kw_unreachable, kw_ret, kw_br, kw_switch, kw_indirectbr, kw_invoke, kw_unwind,
kw_unreachable,
kw_malloc, kw_alloca, kw_free, kw_load, kw_store, kw_getelementptr, kw_malloc, kw_alloca, kw_free, kw_load, kw_store, kw_getelementptr,

10
lib/Bitcode/Reader/BitcodeReader.cpp
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@ -1975,22 +1975,22 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
I = SI; I = SI;
break; break;
} }
case bitc::FUNC_CODE_INST_INDBR: { // INDBR: [opty, op0, op1, ...] case bitc::FUNC_CODE_INST_INDIRECTBR: { // INDIRECTBR: [opty, op0, op1, ...]
if (Record.size() < 2) if (Record.size() < 2)
return Error("Invalid INDBR record"); return Error("Invalid INDIRECTBR record");
const Type *OpTy = getTypeByID(Record[0]); const Type *OpTy = getTypeByID(Record[0]);
Value *Address = getFnValueByID(Record[1], OpTy); Value *Address = getFnValueByID(Record[1], OpTy);
if (OpTy == 0 || Address == 0) if (OpTy == 0 || Address == 0)
return Error("Invalid INDBR record"); return Error("Invalid INDIRECTBR record");
unsigned NumDests = Record.size()-2; unsigned NumDests = Record.size()-2;
IndBrInst *IBI = IndBrInst::Create(Address, NumDests); IndirectBrInst *IBI = IndirectBrInst::Create(Address, NumDests);
InstructionList.push_back(IBI); InstructionList.push_back(IBI);
for (unsigned i = 0, e = NumDests; i != e; ++i) { for (unsigned i = 0, e = NumDests; i != e; ++i) {
if (BasicBlock *DestBB = getBasicBlock(Record[2+i])) { if (BasicBlock *DestBB = getBasicBlock(Record[2+i])) {
IBI->addDestination(DestBB); IBI->addDestination(DestBB);
} else { } else {
delete IBI; delete IBI;
return Error("Invalid INDBR record!"); return Error("Invalid INDIRECTBR record!");
} }
} }
I = IBI; I = IBI;

4
lib/Bitcode/Writer/BitcodeWriter.cpp
View File

@ -1015,8 +1015,8 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
Vals.push_back(VE.getValueID(I.getOperand(i))); Vals.push_back(VE.getValueID(I.getOperand(i)));
break; break;
case Instruction::IndBr: case Instruction::IndirectBr:
Code = bitc::FUNC_CODE_INST_INDBR; Code = bitc::FUNC_CODE_INST_INDIRECTBR;
Vals.push_back(VE.getTypeID(I.getOperand(0)->getType())); Vals.push_back(VE.getTypeID(I.getOperand(0)->getType()));
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
Vals.push_back(VE.getValueID(I.getOperand(i))); Vals.push_back(VE.getValueID(I.getOperand(i)));

2
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -2131,7 +2131,7 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
} }
} }
void SelectionDAGLowering::visitIndBr(IndBrInst &I) { void SelectionDAGLowering::visitIndirectBr(IndirectBrInst &I) {
// Update machine-CFG edges. // Update machine-CFG edges.
for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
CurMBB->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]); CurMBB->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]);

4
lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
View File

@ -49,7 +49,7 @@ class GetElementPtrInst;
class GCFunctionInfo; class GCFunctionInfo;
class ICmpInst; class ICmpInst;
class IntToPtrInst; class IntToPtrInst;
class IndBrInst; class IndirectBrInst;
class InvokeInst; class InvokeInst;
class InsertElementInst; class InsertElementInst;
class InsertValueInst; class InsertValueInst;
@ -449,7 +449,7 @@ private:
void visitRet(ReturnInst &I); void visitRet(ReturnInst &I);
void visitBr(BranchInst &I); void visitBr(BranchInst &I);
void visitSwitch(SwitchInst &I); void visitSwitch(SwitchInst &I);
void visitIndBr(IndBrInst &I); void visitIndirectBr(IndirectBrInst &I);
void visitUnreachable(UnreachableInst &I) { /* noop */ } void visitUnreachable(UnreachableInst &I) { /* noop */ }
// Helpers for visitSwitch // Helpers for visitSwitch

4
lib/Target/CBackend/CBackend.cpp
View File

@ -282,7 +282,7 @@ namespace {
void visitReturnInst(ReturnInst &I); void visitReturnInst(ReturnInst &I);
void visitBranchInst(BranchInst &I); void visitBranchInst(BranchInst &I);
void visitSwitchInst(SwitchInst &I); void visitSwitchInst(SwitchInst &I);
void visitIndBrInst(IndBrInst &I); void visitIndirectBrInst(IndirectBrInst &I);
void visitInvokeInst(InvokeInst &I) { void visitInvokeInst(InvokeInst &I) {
llvm_unreachable("Lowerinvoke pass didn't work!"); llvm_unreachable("Lowerinvoke pass didn't work!");
} }
@ -2579,7 +2579,7 @@ void CWriter::visitSwitchInst(SwitchInst &SI) {
Out << " }\n"; Out << " }\n";
} }
void CWriter::visitIndBrInst(IndBrInst &IBI) { void CWriter::visitIndirectBrInst(IndirectBrInst &IBI) {
Out << " goto *(void*)("; Out << " goto *(void*)(";
writeOperand(IBI.getOperand(0)); writeOperand(IBI.getOperand(0));
Out << ");\n"; Out << ");\n";

6
lib/Target/CppBackend/CPPBackend.cpp
View File

@ -1132,9 +1132,9 @@ namespace {
} }
break; break;
} }
case Instruction::IndBr: { case Instruction::IndirectBr: {
const IndBrInst *IBI = cast<IndBrInst>(I); const IndirectBrInst *IBI = cast<IndirectBrInst>(I);
Out << "IndBrInst *" << iName << " = IndBrInst::Create(" Out << "IndirectBrInst *" << iName << " = IndirectBrInst::Create("
<< opNames[0] << ", " << IBI->getNumDestinations() << ");"; << opNames[0] << ", " << IBI->getNumDestinations() << ");";
nl(Out); nl(Out);
for (unsigned i = 1; i != IBI->getNumOperands(); ++i) { for (unsigned i = 1; i != IBI->getNumOperands(); ++i) {

4
lib/VMCore/AsmWriter.cpp
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@ -1846,8 +1846,8 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
writeOperand(I.getOperand(op+1), true); writeOperand(I.getOperand(op+1), true);
} }
Out << "\n ]"; Out << "\n ]";
} else if (isa<IndBrInst>(I)) { } else if (isa<IndirectBrInst>(I)) {
// Special case indbr instruction to get formatting nice and correct. // Special case indirectbr instruction to get formatting nice and correct.
Out << ' '; Out << ' ';
writeOperand(Operand, true); writeOperand(Operand, true);
Out << ", "; Out << ", ";

2
lib/VMCore/Instruction.cpp
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@ -103,7 +103,7 @@ const char *Instruction::getOpcodeName(unsigned OpCode) {
case Ret: return "ret"; case Ret: return "ret";
case Br: return "br"; case Br: return "br";
case Switch: return "switch"; case Switch: return "switch";
case IndBr: return "indbr"; case IndirectBr: return "indirectbr";
case Invoke: return "invoke"; case Invoke: return "invoke";
case Unwind: return "unwind"; case Unwind: return "unwind";
case Unreachable: return "unreachable"; case Unreachable: return "unreachable";

37
lib/VMCore/Instructions.cpp
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@ -3090,7 +3090,7 @@ void SwitchInst::setSuccessorV(unsigned idx, BasicBlock *B) {
// SwitchInst Implementation // SwitchInst Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
void IndBrInst::init(Value *Address, unsigned NumDests) { void IndirectBrInst::init(Value *Address, unsigned NumDests) {
assert(Address); assert(Address);
ReservedSpace = 1+NumDests; ReservedSpace = 1+NumDests;
NumOperands = 1; NumOperands = 1;
@ -3107,7 +3107,7 @@ void IndBrInst::init(Value *Address, unsigned NumDests) {
/// 2. If NumOps > NumOperands, reserve space for NumOps operands. /// 2. If NumOps > NumOperands, reserve space for NumOps operands.
/// 3. If NumOps == NumOperands, trim the reserved space. /// 3. If NumOps == NumOperands, trim the reserved space.
/// ///
void IndBrInst::resizeOperands(unsigned NumOps) { void IndirectBrInst::resizeOperands(unsigned NumOps) {
unsigned e = getNumOperands(); unsigned e = getNumOperands();
if (NumOps == 0) { if (NumOps == 0) {
NumOps = e*2; NumOps = e*2;
@ -3129,21 +3129,22 @@ void IndBrInst::resizeOperands(unsigned NumOps) {
if (OldOps) Use::zap(OldOps, OldOps + e, true); if (OldOps) Use::zap(OldOps, OldOps + e, true);
} }
IndBrInst::IndBrInst(Value *Address, unsigned NumCases, IndirectBrInst::IndirectBrInst(Value *Address, unsigned NumCases,
Instruction *InsertBefore) Instruction *InsertBefore)
: TerminatorInst(Type::getVoidTy(Address->getContext()), Instruction::IndBr, : TerminatorInst(Type::getVoidTy(Address->getContext()),Instruction::IndirectBr,
0, 0, InsertBefore) { 0, 0, InsertBefore) {
init(Address, NumCases); init(Address, NumCases);
} }
IndBrInst::IndBrInst(Value *Address, unsigned NumCases, BasicBlock *InsertAtEnd) IndirectBrInst::IndirectBrInst(Value *Address, unsigned NumCases,
: TerminatorInst(Type::getVoidTy(Address->getContext()), Instruction::IndBr, BasicBlock *InsertAtEnd)
: TerminatorInst(Type::getVoidTy(Address->getContext()),Instruction::IndirectBr,
0, 0, InsertAtEnd) { 0, 0, InsertAtEnd) {
init(Address, NumCases); init(Address, NumCases);
} }
IndBrInst::IndBrInst(const IndBrInst &IBI) IndirectBrInst::IndirectBrInst(const IndirectBrInst &IBI)
: TerminatorInst(Type::getVoidTy(IBI.getContext()), Instruction::IndBr, : TerminatorInst(Type::getVoidTy(IBI.getContext()), Instruction::IndirectBr,
allocHungoffUses(IBI.getNumOperands()), allocHungoffUses(IBI.getNumOperands()),
IBI.getNumOperands()) { IBI.getNumOperands()) {
Use *OL = OperandList, *InOL = IBI.OperandList; Use *OL = OperandList, *InOL = IBI.OperandList;
@ -3152,13 +3153,13 @@ IndBrInst::IndBrInst(const IndBrInst &IBI)
SubclassOptionalData = IBI.SubclassOptionalData; SubclassOptionalData = IBI.SubclassOptionalData;
} }
IndBrInst::~IndBrInst() { IndirectBrInst::~IndirectBrInst() {
dropHungoffUses(OperandList); dropHungoffUses(OperandList);
} }
/// addDestination - Add a destination. /// addDestination - Add a destination.
/// ///
void IndBrInst::addDestination(BasicBlock *DestBB) { void IndirectBrInst::addDestination(BasicBlock *DestBB) {
unsigned OpNo = NumOperands; unsigned OpNo = NumOperands;
if (OpNo+1 > ReservedSpace) if (OpNo+1 > ReservedSpace)
resizeOperands(0); // Get more space! resizeOperands(0); // Get more space!
@ -3169,8 +3170,8 @@ void IndBrInst::addDestination(BasicBlock *DestBB) {
} }
/// removeDestination - This method removes the specified successor from the /// removeDestination - This method removes the specified successor from the
/// indbr instruction. /// indirectbr instruction.
void IndBrInst::removeDestination(unsigned idx) { void IndirectBrInst::removeDestination(unsigned idx) {
assert(idx < getNumOperands()-1 && "Successor index out of range!"); assert(idx < getNumOperands()-1 && "Successor index out of range!");
unsigned NumOps = getNumOperands(); unsigned NumOps = getNumOperands();
@ -3184,13 +3185,13 @@ void IndBrInst::removeDestination(unsigned idx) {
NumOperands = NumOps-1; NumOperands = NumOps-1;
} }
BasicBlock *IndBrInst::getSuccessorV(unsigned idx) const { BasicBlock *IndirectBrInst::getSuccessorV(unsigned idx) const {
return getSuccessor(idx); return getSuccessor(idx);
} }
unsigned IndBrInst::getNumSuccessorsV() const { unsigned IndirectBrInst::getNumSuccessorsV() const {
return getNumSuccessors(); return getNumSuccessors();
} }
void IndBrInst::setSuccessorV(unsigned idx, BasicBlock *B) { void IndirectBrInst::setSuccessorV(unsigned idx, BasicBlock *B) {
setSuccessor(idx, B); setSuccessor(idx, B);
} }
@ -3335,8 +3336,8 @@ SwitchInst *SwitchInst::clone_impl() const {
return new SwitchInst(*this); return new SwitchInst(*this);
} }
IndBrInst *IndBrInst::clone_impl() const { IndirectBrInst *IndirectBrInst::clone_impl() const {
return new IndBrInst(*this); return new IndirectBrInst(*this);
} }

6
test/Feature/terminators.ll
View File

@ -27,11 +27,11 @@ Case4: ; preds = %0
define i32 @indbrtest(i8* %P, i32* %Q) { define i32 @indbrtest(i8* %P, i32* %Q) {
indbr i8* %P, [label %BB1, label %BB2, label %BB3] indirectbr i8* %P, [label %BB1, label %BB2, label %BB3]
BB1: BB1:
indbr i32* %Q, [] indirectbr i32* %Q, []
BB2: BB2:
indbr i32* %Q, [label %BB1, label %BB2] indirectbr i32* %Q, [label %BB1, label %BB2]
BB3: BB3:
ret i32 2 ret i32 2
} }