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[mips] Refactor arithmetic and logic instructions with immediate operands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-20 03:40:03 +00:00
parent 23a3da0113
commit ab48c503e2
3 changed files with 39 additions and 22 deletions
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22
lib/Target/Mips/Mips64InstrInfo.td
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@ -83,15 +83,19 @@ let usesCustomInserter = 1, Predicates = [HasStdEnc],
//===----------------------------------------------------------------------===//
let DecoderNamespace = "Mips64" in {
/// Arithmetic Instructions (ALU Immediate)
def DADDi : ArithLogicI<0x18, "daddi", simm16_64, immSExt16, CPU64Regs>;
def DADDiu : ArithLogicI<0x19, "daddiu", simm16_64, immSExt16, CPU64Regs,
add>, IsAsCheapAsAMove;
def DANDi : ArithLogicI<0x0c, "andi", uimm16_64, immZExt16, CPU64Regs, and>;
def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
def ORi64 : ArithLogicI<0x0d, "ori", uimm16_64, immZExt16, CPU64Regs, or>;
def XORi64 : ArithLogicI<0x0e, "xori", uimm16_64, immZExt16, CPU64Regs, xor>;
def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
def DADDi : ArithLogicI<"daddi", simm16_64, immSExt16, CPU64Regs>,
ADDI_FM<0x18>;
def DADDiu : ArithLogicI<"daddiu", simm16_64, immSExt16, CPU64Regs, add>,
ADDI_FM<0x19>, IsAsCheapAsAMove;
def DANDi : ArithLogicI<"andi", uimm16_64, immZExt16, CPU64Regs, and>,
ADDI_FM<0xc>;
def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
def ORi64 : ArithLogicI<"ori", uimm16_64, immZExt16, CPU64Regs, or>,
ADDI_FM<0xd>;
def XORi64 : ArithLogicI<"xori", uimm16_64, immZExt16, CPU64Regs, xor>,
ADDI_FM<0xe>;
def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
/// Arithmetic Instructions (3-Operand, R-Type)
def DADD : ArithLogicR<"dadd", IIAlu, CPU64Regs, 1>, ADD_FM<0, 0x2c>;

13
lib/Target/Mips/MipsInstrFormats.td
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@ -207,6 +207,19 @@ class ADD_FM<bits<6> op, bits<6> funct> {
let Inst{5-0} = funct;
}
class ADDI_FM<bits<6> op> {
bits<5> rs;
bits<5> rt;
bits<16> imm16;
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rs;
let Inst{20-16} = rt;
let Inst{15-0} = imm16;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

26
lib/Target/Mips/MipsInstrInfo.td
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@ -355,11 +355,11 @@ class ArithLogicR<string opstr, InstrItinClass Itin, RegisterClass RC,
}
// Arithmetic and logical instructions with 2 register operands.
class ArithLogicI<bits<6> op, string instr_asm, Operand Od, PatLeaf imm_type,
class ArithLogicI<string opstr, Operand Od, PatLeaf imm_type,
RegisterClass RC, SDPatternOperator OpNode = null_frag> :
FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
!strconcat(instr_asm, "\t$rt, $rs, $imm16"),
[(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16),
!strconcat(opstr, "\t$rt, $rs, $imm16"),
[(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> {
let isReMaterializable = 1;
}
@ -917,15 +917,15 @@ def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
//===----------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate)
def ADDiu : ArithLogicI<0x09, "addiu", simm16, immSExt16, CPURegs, add>,
IsAsCheapAsAMove;
def ADDi : ArithLogicI<0x08, "addi", simm16, immSExt16, CPURegs>;
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
def ANDi : ArithLogicI<0x0c, "andi", uimm16, immZExt16, CPURegs, and>;
def ORi : ArithLogicI<0x0d, "ori", uimm16, immZExt16, CPURegs, or>;
def XORi : ArithLogicI<0x0e, "xori", uimm16, immZExt16, CPURegs, xor>;
def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
def ADDiu : ArithLogicI<"addiu", simm16, immSExt16, CPURegs, add>,
ADDI_FM<0x9>, IsAsCheapAsAMove;
def ADDi : ArithLogicI<"addi", simm16, immSExt16, CPURegs>, ADDI_FM<0x8>;
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
def ANDi : ArithLogicI<"andi", uimm16, immZExt16, CPURegs, and>, ADDI_FM<0xc>;
def ORi : ArithLogicI<"ori", uimm16, immZExt16, CPURegs, or>, ADDI_FM<0xd>;
def XORi : ArithLogicI<"xori", uimm16, immZExt16, CPURegs, xor>, ADDI_FM<0xe>;
def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
/// Arithmetic Instructions (3-Operand, R-Type)
def ADDu : ArithLogicR<"addu", IIAlu, CPURegs, 1, add>, ADD_FM<0, 0x21>;