mirror of
https://github.com/RPCS3/llvm.git
synced 2025-02-24 04:32:09 +00:00
Separate AVXCC and SSECC printing for cmpps/pd/ss/sd and add masking before the switch statement. This keeps the unreachable default case from being hit if the instruction was created with an intrinsic with too large of an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165483 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
7c8998eaba
commit
ac0740f244
@ -59,7 +59,8 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
|
||||
|
||||
void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
switch (MI->getOperand(Op).getImm()) {
|
||||
int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
|
||||
switch (Imm) {
|
||||
default: llvm_unreachable("Invalid ssecc argument!");
|
||||
case 0: O << "eq"; break;
|
||||
case 1: O << "lt"; break;
|
||||
@ -77,6 +78,30 @@ void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
|
||||
case 0xd: O << "ge"; break;
|
||||
case 0xe: O << "gt"; break;
|
||||
case 0xf: O << "true"; break;
|
||||
}
|
||||
}
|
||||
|
||||
void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
|
||||
switch (Imm) {
|
||||
default: llvm_unreachable("Invalid avxcc argument!");
|
||||
case 0: O << "eq"; break;
|
||||
case 1: O << "lt"; break;
|
||||
case 2: O << "le"; break;
|
||||
case 3: O << "unord"; break;
|
||||
case 4: O << "neq"; break;
|
||||
case 5: O << "nlt"; break;
|
||||
case 6: O << "nle"; break;
|
||||
case 7: O << "ord"; break;
|
||||
case 8: O << "eq_uq"; break;
|
||||
case 9: O << "nge"; break;
|
||||
case 0xa: O << "ngt"; break;
|
||||
case 0xb: O << "false"; break;
|
||||
case 0xc: O << "neq_oq"; break;
|
||||
case 0xd: O << "ge"; break;
|
||||
case 0xe: O << "gt"; break;
|
||||
case 0xf: O << "true"; break;
|
||||
case 0x10: O << "eq_os"; break;
|
||||
case 0x11: O << "lt_oq"; break;
|
||||
case 0x12: O << "le_oq"; break;
|
||||
|
@ -40,6 +40,7 @@ public:
|
||||
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
|
||||
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
|
||||
void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
|
||||
void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
|
||||
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
|
||||
|
||||
void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
|
||||
|
@ -51,7 +51,8 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
|
||||
|
||||
void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
switch (MI->getOperand(Op).getImm()) {
|
||||
int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
|
||||
switch (Imm) {
|
||||
default: llvm_unreachable("Invalid ssecc argument!");
|
||||
case 0: O << "eq"; break;
|
||||
case 1: O << "lt"; break;
|
||||
@ -69,6 +70,30 @@ void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
|
||||
case 0xd: O << "ge"; break;
|
||||
case 0xe: O << "gt"; break;
|
||||
case 0xf: O << "true"; break;
|
||||
}
|
||||
}
|
||||
|
||||
void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
|
||||
switch (Imm) {
|
||||
default: llvm_unreachable("Invalid avxcc argument!");
|
||||
case 0: O << "eq"; break;
|
||||
case 1: O << "lt"; break;
|
||||
case 2: O << "le"; break;
|
||||
case 3: O << "unord"; break;
|
||||
case 4: O << "neq"; break;
|
||||
case 5: O << "nlt"; break;
|
||||
case 6: O << "nle"; break;
|
||||
case 7: O << "ord"; break;
|
||||
case 8: O << "eq_uq"; break;
|
||||
case 9: O << "nge"; break;
|
||||
case 0xa: O << "ngt"; break;
|
||||
case 0xb: O << "false"; break;
|
||||
case 0xc: O << "neq_oq"; break;
|
||||
case 0xd: O << "ge"; break;
|
||||
case 0xe: O << "gt"; break;
|
||||
case 0xf: O << "true"; break;
|
||||
case 0x10: O << "eq_os"; break;
|
||||
case 0x11: O << "lt_oq"; break;
|
||||
case 0x12: O << "le_oq"; break;
|
||||
@ -85,7 +110,6 @@ void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
|
||||
case 0x1d: O << "ge_oq"; break;
|
||||
case 0x1e: O << "gt_oq"; break;
|
||||
case 0x1f: O << "true_us"; break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -37,6 +37,7 @@ public:
|
||||
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
|
||||
void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
|
||||
void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
|
||||
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
|
||||
void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
|
||||
|
@ -418,7 +418,7 @@ def SSECC : Operand<i8> {
|
||||
}
|
||||
|
||||
def AVXCC : Operand<i8> {
|
||||
let PrintMethod = "printSSECC";
|
||||
let PrintMethod = "printAVXCC";
|
||||
let OperandType = "OPERAND_IMMEDIATE";
|
||||
}
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user