diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 75f57611126..a6851abba78 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2795,15 +2795,48 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
                                               Node->getOperand(2), dl));
     break;
   case ISD::VECTOR_SHUFFLE: {
-    SmallVector<int, 8> Mask;
+    SmallVector<int, 32> Mask(32U, -1);
     cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
 
     EVT VT = Node->getValueType(0);
     EVT EltVT = VT.getVectorElementType();
-    if (!TLI.isTypeLegal(EltVT))
+    SDValue Op0 = Node->getOperand(0);
+    SDValue Op1 = Node->getOperand(1);
+    if (!TLI.isTypeLegal(EltVT)) {
+
       EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
+      
+      // Convert shuffle node
+      // If original node was v4i64 and the new EltVT is i32,
+      // cast operands to v8i32 and re-build the mask
+      unsigned OldNumElems = VT.getVectorNumElements();
+      // Calculate new VT
+      VT = EVT::getVectorVT(*DAG.getContext(), EltVT, VT.getSizeInBits()/EltVT.getSizeInBits());
+      
+      // cast operands to new VT
+      Op0 = DAG.getNode(ISD::BITCAST, dl, VT, Op0);
+      Op1 = DAG.getNode(ISD::BITCAST, dl, VT, Op1);
+	    
+      // Convert the shuffle mask
+	    unsigned int factor = VT.getVectorNumElements()/OldNumElems;
+      // assume that EltVT gets smaller
+      assert(factor > 0);
+      SmallVector<int, 32> NewMask(32U, -1);
+
+      for (unsigned i = 0; i < OldNumElems; ++i) {
+        if (Mask[i] < 0) {
+          for (unsigned fi = 0; fi < factor; ++fi)
+              NewMask[i*factor+fi] = Mask[i];
+        }
+        else {
+          for (unsigned fi = 0; fi < factor; ++fi)
+              NewMask[i*factor+fi] = Mask[i]*factor+fi;
+        }
+        Mask = NewMask;
+      }
+    }    
     unsigned NumElems = VT.getVectorNumElements();
-    SmallVector<SDValue, 8> Ops;
+    SmallVector<SDValue, 16> Ops;
     for (unsigned i = 0; i != NumElems; ++i) {
       if (Mask[i] < 0) {
         Ops.push_back(DAG.getUNDEF(EltVT));
@@ -2812,13 +2845,14 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
       unsigned Idx = Mask[i];
       if (Idx < NumElems)
         Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
-                                  Node->getOperand(0),
+                                  Op0,
                                   DAG.getIntPtrConstant(Idx)));
       else
         Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
-                                  Node->getOperand(1),
+                                  Op1,
                                   DAG.getIntPtrConstant(Idx - NumElems)));
     }
+    
     Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
     Results.push_back(Tmp1);
     break;
diff --git a/test/CodeGen/X86/avx-shuffle-x86_32.ll b/test/CodeGen/X86/avx-shuffle-x86_32.ll
new file mode 100755
index 00000000000..210287f57f2
--- /dev/null
+++ b/test/CodeGen/X86/avx-shuffle-x86_32.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+
+define <4 x i64> @test1(<4 x i64> %a) nounwind {
+ %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ ret <4 x i64>%b
+ ; CHECK test1:
+ ; CHECK: vinsertf128
+ }