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Apply again changes to support ARM memory asm parsing. I removed

Browse Source 
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-03-31 23:26:08 +00:00
parent 842759662b
commit ae0855401b
10 changed files with 364 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/ARM/ARMAddressingModes.h
View File

@ -408,16 +408,18 @@ namespace ARM_AM {
//
// The first operand is always a Reg. The second operand is a reg if in
// reg/reg form, otherwise it's reg#0. The third field encodes the operation
// in bit 12, the immediate in bits 0-11, and the shift op in 13-15.
// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
// forth operand 16-17 encodes the index mode.
//
// If this addressing mode is a frame index (before prolog/epilog insertion
// and code rewriting), this operand will have the form: FI#, reg0, <offs>
// with no shift amount for the frame offset.
//
static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) {
static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
unsigned IdxMode = 0) {
assert(Imm12 < (1 << 12) && "Imm too large!");
bool isSub = Opc == sub;
return Imm12 | ((int)isSub << 12) | (SO << 13);
return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
}
static inline unsigned getAM2Offset(unsigned AM2Opc) {
return AM2Opc & ((1 << 12)-1);
@ -426,7 +428,10 @@ namespace ARM_AM {
return ((AM2Opc >> 12) & 1) ? sub : add;
}
static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
return (ShiftOpc)(AM2Opc >> 13);
return (ShiftOpc)((AM2Opc >> 13) & 7);
}
static inline unsigned getAM2IdxMode(unsigned AM2Opc) {
return (AM2Opc >> 16);
}

53
lib/Target/ARM/ARMBaseInfo.h
View File

@ -200,6 +200,59 @@ inline static unsigned getARMRegisterNumbering(unsigned Reg) {
}
namespace ARMII {
/// ARM Index Modes
enum IndexMode {
IndexModeNone = 0,
IndexModePre = 1,
IndexModePost = 2,
IndexModeUpd = 3
};
/// ARM Addressing Modes
enum AddrMode {
AddrModeNone = 0,
AddrMode1 = 1,
AddrMode2 = 2,
AddrMode3 = 3,
AddrMode4 = 4,
AddrMode5 = 5,
AddrMode6 = 6,
AddrModeT1_1 = 7,
AddrModeT1_2 = 8,
AddrModeT1_4 = 9,
AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
AddrModeT2_i12 = 11,
AddrModeT2_i8 = 12,
AddrModeT2_so = 13,
AddrModeT2_pc = 14, // +/- i12 for pc relative data
AddrModeT2_i8s4 = 15, // i8 * 4
AddrMode_i12 = 16
};
inline static const char *AddrModeToString(AddrMode addrmode) {
switch (addrmode) {
default: llvm_unreachable("Unknown memory operation");
case AddrModeNone: return "AddrModeNone";
case AddrMode1: return "AddrMode1";
case AddrMode2: return "AddrMode2";
case AddrMode3: return "AddrMode3";
case AddrMode4: return "AddrMode4";
case AddrMode5: return "AddrMode5";
case AddrMode6: return "AddrMode6";
case AddrModeT1_1: return "AddrModeT1_1";
case AddrModeT1_2: return "AddrModeT1_2";
case AddrModeT1_4: return "AddrModeT1_4";
case AddrModeT1_s: return "AddrModeT1_s";
case AddrModeT2_i12: return "AddrModeT2_i12";
case AddrModeT2_i8: return "AddrModeT2_i8";
case AddrModeT2_so: return "AddrModeT2_so";
case AddrModeT2_pc: return "AddrModeT2_pc";
case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
case AddrMode_i12: return "AddrMode_i12";
}
}
/// Target Operand Flag enum.
enum TOF {
//===------------------------------------------------------------------===//

24
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -34,25 +34,7 @@ namespace ARMII {
//===------------------------------------------------------------------===//
// This four-bit field describes the addressing mode used.
AddrModeMask = 0x1f,
AddrModeNone = 0,
AddrMode1 = 1,
AddrMode2 = 2,
AddrMode3 = 3,
AddrMode4 = 4,
AddrMode5 = 5,
AddrMode6 = 6,
AddrModeT1_1 = 7,
AddrModeT1_2 = 8,
AddrModeT1_4 = 9,
AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
AddrModeT2_i12 = 11,
AddrModeT2_i8 = 12,
AddrModeT2_so = 13,
AddrModeT2_pc = 14, // +/- i12 for pc relative data
AddrModeT2_i8s4 = 15, // i8 * 4
AddrMode_i12 = 16,
AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
// Size* - Flags to keep track of the size of an instruction.
SizeShift = 5,
@ -64,11 +46,9 @@ namespace ARMII {
// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
// and store ops only. Generic "updating" flag is used for ld/st multiple.
// The index mode enums are declared in ARMBaseInfo.h
IndexModeShift = 8,
IndexModeMask = 3 << IndexModeShift,
IndexModePre = 1,
IndexModePost = 2,
IndexModeUpd = 3,
//===------------------------------------------------------------------===//
// Instruction encoding formats.

18
lib/Target/ARM/ARMInstrFormats.td
View File

@ -525,6 +525,24 @@ class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
let Inst{19-16} = Rn;
let Inst{11-0} = offset{11-0};
}
// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
// but for now use this class for STRT and STRBT.
class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
IndexMode im, Format f, InstrItinClass itin, string opc,
string asm, string cstr, list<dag> pattern>
: AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
pattern> {
// AM2 store w/ two operands: (GPR, am2offset)
// {17-14} Rn
// {13} 1 == Rm, 0 == imm12
// {12} isAdd
// {11-0} imm12/Rm
bits<18> addr;
let Inst{25} = addr{13};
let Inst{23} = addr{12};
let Inst{19-16} = addr{17-14};
let Inst{11-0} = addr{11-0};
}
// addrmode3 instructions
class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,

83
lib/Target/ARM/ARMInstrInfo.td
View File

@ -498,6 +498,12 @@ def ldst_so_reg : Operand<i32>,
let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
}
def MemMode2AsmOperand : AsmOperandClass {
let Name = "MemMode2";
let SuperClasses = [];
let ParserMethod = "tryParseMemMode2Operand";
}
// addrmode2 := reg +/- imm12
// := reg +/- reg shop imm
//
@ -505,6 +511,7 @@ def addrmode2 : Operand<i32>,
ComplexPattern<i32, 3, "SelectAddrMode2", []> {
let EncoderMethod = "getAddrMode2OpValue";
let PrintMethod = "printAddrMode2Operand";
let ParserMatchClass = MemMode2AsmOperand;
let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
}
@ -1668,6 +1675,7 @@ multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
let Inst{23} = addr{12};
let Inst{19-16} = addr{17-14};
let Inst{11-0} = addr{11-0};
let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
}
def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins GPR:$Rn, am2offset:$offset),
@ -1726,17 +1734,35 @@ defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
let mayLoad = 1, neverHasSideEffects = 1 in {
def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, am2offset:$offset), IndexModePost,
LdFrm, IIC_iLoad_ru,
"ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
(ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
"ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
// {17-14} Rn
// {13} 1 == Rm, 0 == imm12
// {12} isAdd
// {11-0} imm12/Rm
bits<18> addr;
let Inst{25} = addr{13};
let Inst{23} = addr{12};
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr{17-14};
let Inst{11-0} = addr{11-0};
let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
}
def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, am2offset:$offset), IndexModePost,
LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
(ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
// {17-14} Rn
// {13} 1 == Rm, 0 == imm12
// {12} isAdd
// {11-0} imm12/Rm
bits<18> addr;
let Inst{25} = addr{13};
let Inst{23} = addr{12};
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr{17-14};
let Inst{11-0} = addr{11-0};
let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
}
def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, am3offset:$offset), IndexModePost,
@ -1830,20 +1856,20 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
// STRT, STRBT, and STRHT are for disassembly only.
def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
IndexModePost, StFrm, IIC_iStore_ru,
"strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
let Inst{21} = 1; // overwrite
}
def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
IndexModePost, StFrm, IIC_iStore_ru,
"strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
let Inst{21} = 1; // overwrite
let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
}
def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
let Inst{21} = 1; // overwrite
let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
}
def STRHT: AI3sthpo<(outs GPR:$base_wb),
@ -3403,8 +3429,9 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
let Inst{23-20} = opc1;
}
class ACI<dag oops, dag iops, string opc, string asm>
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
class ACI<dag oops, dag iops, string opc, string asm,
IndexMode im = IndexModeNone>
: I<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
opc, asm, "", [/* For disassembly only; pattern left blank */]> {
let Inst{27-25} = 0b110;
}
@ -3423,7 +3450,7 @@ multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
def _PRE : ACI<(outs),
(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
opc, "\tp$cop, cr$CRd, $addr!"> {
opc, "\tp$cop, cr$CRd, $addr!", IndexModePre> {
let Inst{31-28} = op31_28;
let Inst{24} = 1; // P = 1
let Inst{21} = 1; // W = 1
@ -3432,8 +3459,8 @@ multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
}
def _POST : ACI<(outs),
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
opc, "\tp$cop, cr$CRd, [$base], $offset"> {
(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
opc, "\tp$cop, cr$CRd, $addr", IndexModePost> {
let Inst{31-28} = op31_28;
let Inst{24} = 0; // P = 0
let Inst{21} = 1; // W = 1
@ -3464,7 +3491,7 @@ multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
def L_PRE : ACI<(outs),
(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
!strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
!strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
let Inst{31-28} = op31_28;
let Inst{24} = 1; // P = 1
let Inst{21} = 1; // W = 1
@ -3473,8 +3500,8 @@ multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
}
def L_POST : ACI<(outs),
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
!strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
!strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr", IndexModePost> {
let Inst{31-28} = op31_28;
let Inst{24} = 0; // P = 0
let Inst{21} = 1; // W = 1

146
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -48,7 +48,8 @@ class ARMAsmParser : public TargetAsmParser {
bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
bool TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
ARMII::AddrMode AddrMode);
bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
@ -95,6 +96,14 @@ class ARMAsmParser : public TargetAsmParser {
SmallVectorImpl<MCParsedAsmOperand*>&);
OperandMatchResultTy tryParseMSRMaskOperand(
SmallVectorImpl<MCParsedAsmOperand*>&);
OperandMatchResultTy tryParseMemMode2Operand(
SmallVectorImpl<MCParsedAsmOperand*>&);
// Asm Match Converter Methods
bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &);
bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &);
public:
ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
@ -172,6 +181,7 @@ class ARMOperand : public MCParsedAsmOperand {
/// Combined record for all forms of ARM address expressions.
struct {
ARMII::AddrMode AddrMode;
unsigned BaseRegNum;
union {
unsigned RegNum; ///< Offset register num, when OffsetIsReg.
@ -293,7 +303,9 @@ public:
/// @name Memory Operand Accessors
/// @{
ARMII::AddrMode getMemAddrMode() const {
return Mem.AddrMode;
}
unsigned getMemBaseRegNum() const {
return Mem.BaseRegNum;
}
@ -338,6 +350,27 @@ public:
bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
bool isMemory() const { return Kind == Memory; }
bool isShifter() const { return Kind == Shifter; }
bool isMemMode2() const {
if (getMemAddrMode() != ARMII::AddrMode2)
return false;
if (getMemOffsetIsReg())
return true;
if (getMemNegative() &&
!(getMemPostindexed() || getMemPreindexed()))
return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
if (!CE) return false;
int64_t Value = CE->getValue();
// The offset must be in the range 0-4095 (imm12).
if (Value > 4095 || Value < -4095)
return false;
return true;
}
bool isMemMode5() const {
if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
getMemNegative())
@ -465,6 +498,47 @@ public:
"No offset operand support in mode 7");
}
void addMemMode2Operands(MCInst &Inst, unsigned N) const {
assert(isMemMode2() && "Invalid mode or number of operands!");
Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
if (getMemOffsetIsReg()) {
Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
int64_t ShiftAmount = 0;
if (getMemOffsetRegShifted()) {
ShOpc = getMemShiftType();
const MCConstantExpr *CE =
dyn_cast<MCConstantExpr>(getMemShiftAmount());
ShiftAmount = CE->getValue();
}
Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
ShOpc, IdxMode)));
return;
}
// Create a operand placeholder to always yield the same number of operands.
Inst.addOperand(MCOperand::CreateReg(0));
// FIXME: #-0 is encoded differently than #0. Does the parser preserve
// the difference?
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
assert(CE && "Non-constant mode 2 offset operand!");
int64_t Offset = CE->getValue();
if (Offset >= 0)
Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
Offset, ARM_AM::no_shift, IdxMode)));
else
Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
-Offset, ARM_AM::no_shift, IdxMode)));
}
void addMemMode5Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && isMemMode5() && "Invalid number of operands!");
@ -599,9 +673,9 @@ public:
return Op;
}
static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
const MCExpr *Offset, int OffsetRegNum,
bool OffsetRegShifted,
static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
bool OffsetIsReg, const MCExpr *Offset,
int OffsetRegNum, bool OffsetRegShifted,
enum ARM_AM::ShiftOpc ShiftType,
const MCExpr *ShiftAmount, bool Preindexed,
bool Postindexed, bool Negative, bool Writeback,
@ -618,6 +692,7 @@ public:
"Cannot have expression offset and register offset!");
ARMOperand *Op = new ARMOperand(Memory);
Op->Mem.AddrMode = AddrMode;
Op->Mem.BaseRegNum = BaseRegNum;
Op->Mem.OffsetIsReg = OffsetIsReg;
if (OffsetIsReg)
@ -689,7 +764,8 @@ void ARMOperand::dump(raw_ostream &OS) const {
break;
case Memory:
OS << "<memory "
<< "base:" << getMemBaseRegNum();
<< "am:" << ARMII::AddrModeToString(getMemAddrMode())
<< " base:" << getMemBaseRegNum();
if (getMemOffsetIsReg()) {
OS << " offset:<register " << getMemOffsetRegNum();
if (getMemOffsetRegShifted()) {
@ -1132,13 +1208,57 @@ tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return MatchOperand_Success;
}
/// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::LBrac) && "Token is not a \"[\"");
if (ParseMemory(Operands, ARMII::AddrMode2))
return MatchOperand_NoMatch;
return MatchOperand_Success;
}
/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
bool ARMAsmParser::
CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
return true;
}
/// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
bool ARMAsmParser::
CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
return true;
}
/// Parse an ARM memory expression, return false if successful else return true
/// or an error. The first token must be a '[' when called.
///
/// TODO Only preindexing and postindexing addressing are started, unindexed
/// with option, etc are still to do.
bool ARMAsmParser::
ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
SMLoc S, E;
assert(Parser.getTok().is(AsmToken::LBrac) &&
"Token is not a Left Bracket");
@ -1196,6 +1316,9 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
ExclaimTok.getLoc());
Writeback = true;
Parser.Lex(); // Eat exclaim token
} else { // In addressing mode 2, pre-indexed mode always end with "!"
if (AddrMode == ARMII::AddrMode2)
Preindexed = false;
}
} else {
// The "[Rn" we have so far was not followed by a comma.
@ -1231,11 +1354,10 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Offset = MCConstantExpr::Create(0, getContext());
}
Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
OffsetRegNum, OffsetRegShifted,
ShiftType, ShiftAmount, Preindexed,
Postindexed, Negative, Writeback,
S, E));
Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
Offset, OffsetRegNum, OffsetRegShifted,
ShiftType, ShiftAmount, Preindexed,
Postindexed, Negative, Writeback, S, E));
if (WBOp)
Operands.push_back(WBOp);

12
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -643,8 +643,11 @@ static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
if (PW) {
MI.addOperand(MCOperand::CreateReg(0));
ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
const TargetInstrDesc &TID = ARMInsts[Opcode];
unsigned IndexMode =
(TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
ARM_AM::no_shift);
ARM_AM::no_shift, IndexMode);
MI.addOperand(MCOperand::CreateImm(Offset));
OpIdx = 5;
} else {
@ -1084,6 +1087,8 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
return false;
ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
unsigned IndexMode =
(TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
if (getIBit(insn) == 0) {
// For pre- and post-indexed case, add a reg0 operand (Addressing Mode #2).
// Otherwise, skip the reg operand since for addrmode_imm12, Rn has already
@ -1095,7 +1100,8 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Disassemble the 12-bit immediate offset.
unsigned Imm12 = slice(insn, 11, 0);
unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift,
IndexMode);
MI.addOperand(MCOperand::CreateImm(Offset));
OpIdx += 1;
} else {
@ -1110,7 +1116,7 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// A8.4.1. Possible rrx or shift amount of 32...
getImmShiftSE(ShOp, ShImm);
MI.addOperand(MCOperand::CreateImm(
ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp, IndexMode)));
OpIdx += 2;
}

54
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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@ -181,18 +181,12 @@ void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
}
}
void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
raw_ostream &O) {
void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
raw_ostream &O) {
const MCOperand &MO1 = MI->getOperand(Op);
const MCOperand &MO2 = MI->getOperand(Op+1);
const MCOperand &MO3 = MI->getOperand(Op+2);
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op, O);
return;
}
O << "[" << getRegisterName(MO1.getReg());
if (!MO2.getReg()) {
@ -215,6 +209,50 @@ void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
O << "]";
}
void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
raw_ostream &O) {
const MCOperand &MO1 = MI->getOperand(Op);
const MCOperand &MO2 = MI->getOperand(Op+1);
const MCOperand &MO3 = MI->getOperand(Op+2);
O << "[" << getRegisterName(MO1.getReg()) << "], ";
if (!MO2.getReg()) {
unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
O << '#'
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
<< ImmOffs;
return;
}
O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
<< getRegisterName(MO2.getReg());
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
<< " #" << ShImm;
}
void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
raw_ostream &O) {
const MCOperand &MO1 = MI->getOperand(Op);
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op, O);
return;
}
const MCOperand &MO3 = MI->getOperand(Op+2);
unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
if (IdxMode == ARMII::IndexModePost) {
printAM2PostIndexOp(MI, Op, O);
return;
}
printAM2PreOrOffsetIndexOp(MI, Op, O);
}
void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {

4
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
View File

@ -42,7 +42,11 @@ public:
void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);

34
test/MC/ARM/arm_addrmode2.s Normal file
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@ -0,0 +1,34 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
@ Post-indexed
@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
@ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
@ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
@ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
@ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
@ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
@ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
@ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
@ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
@ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
@ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
@ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]
ldrt r1, [r0], r2
ldrt r1, [r0], r2, lsr #3
ldrt r1, [r0], #4
ldrbt r1, [r0], r2
ldrbt r1, [r0], r2, lsr #3
ldrbt r1, [r0], #4
strt r1, [r0], r2
strt r1, [r0], r2, lsr #3
strt r1, [r0], #4
strbt r1, [r0], r2
strbt r1, [r0], r2, lsr #3
strbt r1, [r0], #4
@ Pre-indexed
@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
@ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
ldr r1, [r0, r2, lsr #3]!
ldrb r1, [r0, r2, lsr #3]!