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Fix a major regression last night that prevented us from producing [mem] op= reg
operations. The body of the if is less indented but unmodified in this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19638 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
068a81e9fc
commit
ae3ffba466
@ -2489,128 +2489,130 @@ void ISel::Select(SDOperand N) {
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// Check to see if this is a load/op/store combination.
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if (N.getOperand(1).Val->hasOneUse() &&
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N.getOperand(0).getOpcode() == ISD::LOAD &&
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N.getOperand(1).Val->getNumOperands() == 2 &&
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!MVT::isFloatingPoint(N.getOperand(0).getValue(0).getValueType()) &&
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isFoldableLoad(N.getOperand(0).getValue(0),
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N.getOperand(0).getValue(1))) {
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!MVT::isFloatingPoint(N.getOperand(0).getValue(0).getValueType())) {
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SDOperand TheLoad = N.getOperand(0).getValue(0);
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// See if the stored value is a simple binary operator that uses the load
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// as one of its operands.
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SDOperand Op = N.getOperand(1);
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// Check to see if we are loading the same pointer that we're storing to.
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if (TheLoad.getOperand(1) == N.getOperand(2)) {
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// See if the stored value is a simple binary operator that uses the
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// load as one of its operands.
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SDOperand Op = N.getOperand(1);
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if ((Op.getOperand(0) == TheLoad || Op.getOperand(1) == TheLoad)) {
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// Finally, check to see if this is one of the ops we can handle!
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static const unsigned ADDTAB[] = {
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X86::ADD8mi, X86::ADD16mi, X86::ADD32mi,
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X86::ADD8mr, X86::ADD16mr, X86::ADD32mr,
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};
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static const unsigned SUBTAB[] = {
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X86::SUB8mi, X86::SUB16mi, X86::SUB32mi,
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X86::SUB8mr, X86::SUB16mr, X86::SUB32mr,
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};
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static const unsigned ANDTAB[] = {
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X86::AND8mi, X86::AND16mi, X86::AND32mi,
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X86::AND8mr, X86::AND16mr, X86::AND32mr,
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};
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static const unsigned ORTAB[] = {
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X86::OR8mi, X86::OR16mi, X86::OR32mi,
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X86::OR8mr, X86::OR16mr, X86::OR32mr,
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};
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static const unsigned XORTAB[] = {
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X86::XOR8mi, X86::XOR16mi, X86::XOR32mi,
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X86::XOR8mr, X86::XOR16mr, X86::XOR32mr,
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};
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static const unsigned SHLTAB[] = {
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X86::SHL8mi, X86::SHL16mi, X86::SHL32mi,
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/*Have to put the reg in CL*/0, 0, 0,
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};
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static const unsigned SARTAB[] = {
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X86::SAR8mi, X86::SAR16mi, X86::SAR32mi,
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/*Have to put the reg in CL*/0, 0, 0,
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};
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static const unsigned SHRTAB[] = {
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X86::SHR8mi, X86::SHR16mi, X86::SHR32mi,
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/*Have to put the reg in CL*/0, 0, 0,
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};
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if (TheLoad.getOperand(1) == N.getOperand(2) &&
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((Op.getOperand(0) == TheLoad &&
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isFoldableLoad(TheLoad, Op.getOperand(1))) ||
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(Op.getOperand(1) == TheLoad &&
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isFoldableLoad(TheLoad, Op.getOperand(0))))) {
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// Finally, check to see if this is one of the ops we can handle!
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static const unsigned ADDTAB[] = {
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X86::ADD8mi, X86::ADD16mi, X86::ADD32mi,
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X86::ADD8mr, X86::ADD16mr, X86::ADD32mr,
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};
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static const unsigned SUBTAB[] = {
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X86::SUB8mi, X86::SUB16mi, X86::SUB32mi,
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X86::SUB8mr, X86::SUB16mr, X86::SUB32mr,
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};
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static const unsigned ANDTAB[] = {
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X86::AND8mi, X86::AND16mi, X86::AND32mi,
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X86::AND8mr, X86::AND16mr, X86::AND32mr,
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};
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static const unsigned ORTAB[] = {
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X86::OR8mi, X86::OR16mi, X86::OR32mi,
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X86::OR8mr, X86::OR16mr, X86::OR32mr,
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};
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static const unsigned XORTAB[] = {
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X86::XOR8mi, X86::XOR16mi, X86::XOR32mi,
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X86::XOR8mr, X86::XOR16mr, X86::XOR32mr,
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};
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static const unsigned SHLTAB[] = {
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X86::SHL8mi, X86::SHL16mi, X86::SHL32mi,
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/*Have to put the reg in CL*/0, 0, 0,
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};
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static const unsigned SARTAB[] = {
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X86::SAR8mi, X86::SAR16mi, X86::SAR32mi,
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/*Have to put the reg in CL*/0, 0, 0,
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};
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static const unsigned SHRTAB[] = {
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X86::SHR8mi, X86::SHR16mi, X86::SHR32mi,
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/*Have to put the reg in CL*/0, 0, 0,
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};
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const unsigned *TabPtr = 0;
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switch (Op.getOpcode()) {
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default: std::cerr << "CANNOT [mem] op= val: "; Op.Val->dump(); std::cerr << "\n"; break;
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case ISD::MUL:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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case ISD::UREM: break;
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const unsigned *TabPtr = 0;
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switch (Op.getOpcode()) {
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default: std::cerr << "CANNOT [mem] op= val: "; Op.Val->dump(); std::cerr << "\n"; break;
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case ISD::MUL:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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case ISD::UREM: break;
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case ISD::ADD: TabPtr = ADDTAB; break;
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case ISD::SUB: TabPtr = SUBTAB; break;
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case ISD::AND: TabPtr = ANDTAB; break;
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case ISD:: OR: TabPtr = ORTAB; break;
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case ISD::XOR: TabPtr = XORTAB; break;
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case ISD::SHL: TabPtr = SHLTAB; break;
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case ISD::SRA: TabPtr = SARTAB; break;
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case ISD::SRL: TabPtr = SHRTAB; break;
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}
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case ISD::ADD: TabPtr = ADDTAB; break;
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case ISD::SUB: TabPtr = SUBTAB; break;
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case ISD::AND: TabPtr = ANDTAB; break;
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case ISD:: OR: TabPtr = ORTAB; break;
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case ISD::XOR: TabPtr = XORTAB; break;
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case ISD::SHL: TabPtr = SHLTAB; break;
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case ISD::SRA: TabPtr = SARTAB; break;
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case ISD::SRL: TabPtr = SHRTAB; break;
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}
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if (TabPtr) {
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// Handle: [mem] op= CST
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SDOperand Op0 = Op.getOperand(0);
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SDOperand Op1 = Op.getOperand(1);
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
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switch (Op0.getValueType()) { // Use Op0's type because of shifts.
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default: break;
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case MVT::i1:
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case MVT::i8: Opc = TabPtr[0]; break;
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case MVT::i16: Opc = TabPtr[1]; break;
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case MVT::i32: Opc = TabPtr[2]; break;
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}
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if (Opc) {
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if (getRegPressure(TheLoad.getOperand(0)) >
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getRegPressure(TheLoad.getOperand(1))) {
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Select(TheLoad.getOperand(0));
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SelectAddress(TheLoad.getOperand(1), AM);
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} else {
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SelectAddress(TheLoad.getOperand(1), AM);
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Select(TheLoad.getOperand(0));
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}
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addFullAddress(BuildMI(BB, Opc, 4+1),AM).addImm(CN->getValue());
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return;
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}
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if (TabPtr) {
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// Handle: [mem] op= CST
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SDOperand Op0 = Op.getOperand(0);
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SDOperand Op1 = Op.getOperand(1);
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
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switch (Op0.getValueType()) { // Use Op0's type because of shifts.
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default: break;
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case MVT::i1:
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case MVT::i8: Opc = TabPtr[0]; break;
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case MVT::i16: Opc = TabPtr[1]; break;
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case MVT::i32: Opc = TabPtr[2]; break;
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}
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// If we have [mem] = V op [mem], try to turn it into:
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// [mem] = [mem] op V.
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if (Op1 == TheLoad && Op.getOpcode() != ISD::SUB &&
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Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRA &&
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Op.getOpcode() != ISD::SRL)
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std::swap(Op0, Op1);
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if (Op0 == TheLoad) {
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switch (Op0.getValueType()) {
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default: break;
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case MVT::i1:
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case MVT::i8: Opc = TabPtr[3]; break;
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case MVT::i16: Opc = TabPtr[4]; break;
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case MVT::i32: Opc = TabPtr[5]; break;
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}
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if (Opc) {
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if (Opc) {
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if (getRegPressure(TheLoad.getOperand(0)) >
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getRegPressure(TheLoad.getOperand(1))) {
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Select(TheLoad.getOperand(0));
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SelectAddress(TheLoad.getOperand(1), AM);
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unsigned Reg = SelectExpr(Op1);
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addFullAddress(BuildMI(BB, Opc, 4+1),AM).addReg(Reg);
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return;
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}
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} else {
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SelectAddress(TheLoad.getOperand(1), AM);
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Select(TheLoad.getOperand(0));
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}
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addFullAddress(BuildMI(BB, Opc, 4+1),AM).addImm(CN->getValue());
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return;
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}
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}
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// If we have [mem] = V op [mem], try to turn it into:
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// [mem] = [mem] op V.
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if (Op1 == TheLoad && Op.getOpcode() != ISD::SUB &&
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Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRA &&
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Op.getOpcode() != ISD::SRL)
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std::swap(Op0, Op1);
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if (Op0 == TheLoad) {
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switch (Op0.getValueType()) {
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default: break;
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case MVT::i1:
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case MVT::i8: Opc = TabPtr[3]; break;
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case MVT::i16: Opc = TabPtr[4]; break;
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case MVT::i32: Opc = TabPtr[5]; break;
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}
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if (Opc) {
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Select(TheLoad.getOperand(0));
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SelectAddress(TheLoad.getOperand(1), AM);
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unsigned Reg = SelectExpr(Op1);
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addFullAddress(BuildMI(BB, Opc, 4+1),AM).addReg(Reg);
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return;
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}
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}
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}
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}
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}
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switch (N.getOperand(1).getValueType()) {
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default: assert(0 && "Cannot store this type!");
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case MVT::i1:
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