From aedc637c966b6eaa3ca33e9220efe5ec34517de7 Mon Sep 17 00:00:00 2001 From: Scott Michel Date: Wed, 10 Dec 2008 00:15:19 +0000 Subject: [PATCH] CellSPU: - Fix bug 3185, with misc other cleanups. - Needed to implement SPUInstrInfo::InsertBranch(). CAUTION: Not sure what gets or needs to get passed to InsertBranch() to insert a conditional branch. This will abort for now until a good test case shows up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60811 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../CellSPU/AsmPrinter/SPUAsmPrinter.cpp | 12 + lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 15 +- lib/Target/CellSPU/SPUISelLowering.cpp | 14 +- lib/Target/CellSPU/SPUInstrInfo.cpp | 248 ++++++++++++++---- lib/Target/CellSPU/SPUInstrInfo.h | 12 +- lib/Target/CellSPU/SPUInstrInfo.td | 56 ++-- lib/Target/CellSPU/SPUOperands.td | 7 +- lib/Target/CellSPU/SPUTargetMachine.cpp | 2 + lib/Target/CellSPU/SPUTargetMachine.h | 4 +- 9 files changed, 286 insertions(+), 84 deletions(-) diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 94d8cd5aa3f..589a2600050 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -220,6 +220,18 @@ namespace { } void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo) { + // Used to generate a ".-", but it turns out that the assembler + // really wants the target. + // + // N.B.: This operand is used for call targets. Branch hints are another + // animal entirely. + printOp(MI->getOperand(OpNo)); + } + + void printHBROperand(const MachineInstr *MI, unsigned OpNo) { + // HBR operands are generated in front of branches, hence, the + // program counter plus the target. + O << ".+"; printOp(MI->getOperand(OpNo)); } diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 14f3edd4d6a..9ac0e2e256c 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -557,10 +557,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base, else Addr = N; // Register - if (OpOpc == ISD::STORE) - Offs = Op.getOperand(3); - else - Offs = Op.getOperand(2); // LOAD + Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2)); if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) { if (Offs.getOpcode() == ISD::UNDEF) @@ -570,6 +567,16 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base, Index = Addr; return true; } + } else { + /* If otherwise unadorned, default to D-form address with 0 offset: */ + if (Opc == ISD::CopyFromReg) { + Index = N.getOperand(1); + } else { + Index = N; + } + + Base = CurDAG->getTargetConstant(0, Index.getValueType()); + return true; } } diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 031d068c543..c3c31e0f470 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -28,7 +28,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/CodeGen/SchedulerRegistry.h" #include @@ -131,9 +130,6 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) addRegisterClass(MVT::f64, SPU::R64FPRegisterClass); addRegisterClass(MVT::i128, SPU::GPRCRegisterClass); - // Initialize libcalls: - setLibcallName(RTLIB::MUL_I64, "__muldi3"); - // SPU has no sign or zero extended loads for i1, i8, i16: setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); @@ -237,10 +233,12 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setOperationAction(ISD::MUL, MVT::i64, Expand); // libcall // SMUL_LOHI, UMUL_LOHI - setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); - setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); - setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom); - setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom); +#if 0 + setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); +#endif // Need to custom handle (some) common i8, i64 math ops setOperationAction(ISD::ADD, MVT::i64, Custom); diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index bb89306bd94..442d49141b1 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -21,6 +21,26 @@ using namespace llvm; +namespace { + //! Predicate for an unconditional branch instruction + inline bool isUncondBranch(const MachineInstr *I) { + unsigned opc = I->getOpcode(); + + return (opc == SPU::BR + || opc == SPU::BRA + || opc == SPU::BI); + } + + inline bool isCondBranch(const MachineInstr *I) { + unsigned opc = I->getOpcode(); + + return (opc == SPU::BRNZ + || opc == SPU::BRZ + || opc == SPU::BRHNZ + || opc == SPU::BRHZ); + } +} + SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm) : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])), TM(tm), @@ -131,14 +151,28 @@ SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, case SPU::LQDr128: case SPU::LQDr64: case SPU::LQDr32: - case SPU::LQDr16: + case SPU::LQDr16: { + const MachineOperand MOp1 = MI->getOperand(1); + const MachineOperand MOp2 = MI->getOperand(2); + if (MOp1.isImm() + && (MOp2.isFI() + || (MOp2.isReg() && MOp2.getReg() == SPU::R1))) { + if (MOp2.isFI()) + FrameIndex = MOp2.getIndex(); + else + FrameIndex = MOp1.getImm() / SPUFrameInfo::stackSlotSize(); + return MI->getOperand(0).getReg(); + } + break; + } case SPU::LQXv4i32: case SPU::LQXr128: case SPU::LQXr64: case SPU::LQXr32: case SPU::LQXr16: - if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && - MI->getOperand(2).isFI()) { + if (MI->getOperand(1).isReg() && MI->getOperand(2).isReg() + && (MI->getOperand(2).getReg() == SPU::R1 + || MI->getOperand(1).getReg() == SPU::R1)) { FrameIndex = MI->getOperand(2).getIndex(); return MI->getOperand(0).getReg(); } @@ -161,7 +195,20 @@ SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI, case SPU::STQDr64: case SPU::STQDr32: case SPU::STQDr16: - case SPU::STQDr8: + case SPU::STQDr8: { + const MachineOperand MOp1 = MI->getOperand(1); + const MachineOperand MOp2 = MI->getOperand(2); + if (MOp1.isImm() + && (MOp2.isFI() + || (MOp2.isReg() && MOp2.getReg() == SPU::R1))) { + if (MOp2.isFI()) + FrameIndex = MOp2.getIndex(); + else + FrameIndex = MOp1.getImm() / SPUFrameInfo::stackSlotSize(); + return MI->getOperand(0).getReg(); + } + break; + } case SPU::STQXv16i8: case SPU::STQXv8i16: case SPU::STQXv4i32: @@ -172,8 +219,9 @@ SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI, case SPU::STQXr32: case SPU::STQXr16: case SPU::STQXr8: - if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && - MI->getOperand(2).isFI()) { + if (MI->getOperand(1).isReg() && MI->getOperand(2).isReg() + && (MI->getOperand(2).getReg() == SPU::R1 + || MI->getOperand(1).getReg() == SPU::R1)) { FrameIndex = MI->getOperand(2).getIndex(); return MI->getOperand(0).getReg(); } @@ -193,11 +241,6 @@ bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, // we instruction select bitconvert i64 -> f64 as a noop for example, so our // types have no specific meaning. - //if (DestRC != SrcRC) { - // cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n"; - // abort(); - //} - if (DestRC == SPU::R8CRegisterClass) { BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0); } else if (DestRC == SPU::R16CRegisterClass) { @@ -234,30 +277,21 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, const TargetRegisterClass *RC) const { unsigned opc; + bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset()); if (RC == SPU::GPRCRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr128 - : SPU::STQXr128; + opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128); } else if (RC == SPU::R64CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr64 - : SPU::STQXr64; + opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64); } else if (RC == SPU::R64FPRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr64 - : SPU::STQXr64; + opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64); } else if (RC == SPU::R32CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr32 - : SPU::STQXr32; + opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32); } else if (RC == SPU::R32FPRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr32 - : SPU::STQXr32; + opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32); } else if (RC == SPU::R16CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ? - SPU::STQDr16 - : SPU::STQXr16; + opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16); + } else if (RC == SPU::R8CRegisterClass) { + opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8); } else { assert(0 && "Unknown regclass!"); abort(); @@ -317,30 +351,21 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, const TargetRegisterClass *RC) const { unsigned opc; + bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset()); if (RC == SPU::GPRCRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr128 - : SPU::LQXr128; + opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128); } else if (RC == SPU::R64CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr64 - : SPU::LQXr64; + opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64); } else if (RC == SPU::R64FPRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr64 - : SPU::LQXr64; + opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64); } else if (RC == SPU::R32CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr32 - : SPU::LQXr32; + opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32); } else if (RC == SPU::R32FPRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr32 - : SPU::LQXr32; + opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32); } else if (RC == SPU::R16CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr16 - : SPU::LQXr16; + opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16); + } else if (RC == SPU::R8CRegisterClass) { + opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8); } else { assert(0 && "Unknown regclass in loadRegFromStackSlot!"); abort(); @@ -353,9 +378,9 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, \note We are really pessimistic here about what kind of a load we're doing. */ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const { cerr << "loadRegToAddr() invoked!\n"; abort(); @@ -438,3 +463,126 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, #endif } +//! Branch analysis +/* + \note This code was kiped from PPC. There may be more branch analysis for + CellSPU than what's currently done here. + */ +bool +SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond) const { + // If the block has no terminators, it just falls into the block after it. + MachineBasicBlock::iterator I = MBB.end(); + if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) + return false; + + // Get the last instruction in the block. + MachineInstr *LastInst = I; + + // If there is only one terminator instruction, process it. + if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { + if (isUncondBranch(LastInst)) { + TBB = LastInst->getOperand(0).getMBB(); + return false; + } else if (isCondBranch(LastInst)) { + // Block ends with fall-through condbranch. + TBB = LastInst->getOperand(1).getMBB(); + Cond.push_back(LastInst->getOperand(0)); + Cond.push_back(LastInst->getOperand(1)); + return false; + } + // Otherwise, don't know what this is. + return true; + } + + // Get the instruction before it if it's a terminator. + MachineInstr *SecondLastInst = I; + + // If there are three terminators, we don't know what sort of block this is. + if (SecondLastInst && I != MBB.begin() && + isUnpredicatedTerminator(--I)) + return true; + + // If the block ends with a conditional and unconditional branch, handle it. + if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) { + TBB = SecondLastInst->getOperand(1).getMBB(); + Cond.push_back(SecondLastInst->getOperand(0)); + Cond.push_back(SecondLastInst->getOperand(1)); + FBB = LastInst->getOperand(0).getMBB(); + return false; + } + + // If the block ends with two unconditional branches, handle it. The second + // one is not executed, so remove it. + if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) { + TBB = SecondLastInst->getOperand(0).getMBB(); + I = LastInst; + I->eraseFromParent(); + return false; + } + + // Otherwise, can't handle this. + return true; +} + +unsigned +SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator I = MBB.end(); + if (I == MBB.begin()) + return 0; + --I; + if (!isCondBranch(I) && !isUncondBranch(I)) + return 0; + + // Remove the first branch. + I->eraseFromParent(); + I = MBB.end(); + if (I == MBB.begin()) + return 1; + + --I; + if (isCondBranch(I)) + return 1; + + // Remove the second branch. + I->eraseFromParent(); + return 2; +} + +unsigned +SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + const SmallVectorImpl &Cond) const { + // Shouldn't be a fall through. + assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert((Cond.size() == 2 || Cond.size() == 0) && + "SPU branch conditions have two components!"); + + // One-way branch. + if (FBB == 0) { + if (Cond.empty()) // Unconditional branch + BuildMI(&MBB, get(SPU::BR)).addMBB(TBB); + else { // Conditional branch + /* BuildMI(&MBB, get(SPU::BRNZ)) + .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); */ + cerr << "SPUInstrInfo::InsertBranch conditional branch logic needed\n"; + abort(); + } + return 1; + } + + // Two-way Conditional Branch. +#if 0 + BuildMI(&MBB, get(SPU::BRNZ)) + .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); + BuildMI(&MBB, get(SPU::BR)).addMBB(FBB); +#else + cerr << "SPUInstrInfo::InsertBranch conditional branch logic needed\n"; + abort(); +#endif + + return 2; +} + + diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index 5c59b68cbb1..27766ba4327 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -91,7 +91,17 @@ namespace llvm { MachineInstr* LoadMI) const { return 0; } - }; + + virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond) const; + + virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; + + virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + const SmallVectorImpl &Cond) const; + }; } #endif diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 678f8e9dac2..2338a0318ba 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -1124,7 +1124,7 @@ defm ANDC : AndComplement; class ANDBIInst pattern>: RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val", - IntegerOp, pattern>; + ByteOp, pattern>; multiclass AndByteImm { @@ -1141,7 +1141,7 @@ defm ANDBI : AndByteImm; class ANDHIInst pattern> : RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val", - IntegerOp, pattern>; + ByteOp, pattern>; multiclass AndHalfwordImm { @@ -3394,25 +3394,39 @@ let isTerminator = 1, isBarrier = 1 in { // Single precision floating point instructions //===----------------------------------------------------------------------===// -def FAv4f32: - RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "fa\t$rT, $rA, $rB", SPrecFP, - [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>; +class FAInst pattern>: + RRForm<0b01011000100, OOL, IOL, "fa\t$rT, $rA, $rB", + SPrecFP, pattern>; +class FAVecInst: + FAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (fadd (vectype VECREG:$rA), (vectype VECREG:$rB)))]>; +multiclass SFPAdd +{ + def v4f32: FAVecInst; + def r32: FAInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), + [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>; +} -def FAf32 : - RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), - "fa\t$rT, $rA, $rB", SPrecFP, - [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>; +defm FA : SFPAdd; -def FSv4f32: - RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "fs\t$rT, $rA, $rB", SPrecFP, - [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>; +class FSInst pattern>: + RRForm<0b01011000100, OOL, IOL, "fs\t$rT, $rA, $rB", + SPrecFP, pattern>; -def FSf32 : - RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), - "fs\t$rT, $rA, $rB", SPrecFP, - [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>; +class FSVecInst: + FSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (fsub (vectype VECREG:$rA), (vectype VECREG:$rB)))]>; + +multiclass SFPSub +{ + def v4f32: FSVecInst; + def r32: FSInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), + [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>; +} + +defm FS : SFPSub; // Floating point reciprocal estimate def FREv4f32 : @@ -3841,6 +3855,12 @@ def : Pat<(fabs (v2f64 VECREG:$rA)), (ANDfabsvec (v2f64 VECREG:$rA), (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>; +//===----------------------------------------------------------------------===// +// Hint for branch instructions: +//===----------------------------------------------------------------------===// + +/* def HBR : SPUInstr<(outs), (ins), "hbr\t" */ + //===----------------------------------------------------------------------===// // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong // in the odd pipeline) diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td index 43982279b52..d788f837fc0 100644 --- a/lib/Target/CellSPU/SPUOperands.td +++ b/lib/Target/CellSPU/SPUOperands.td @@ -575,7 +575,7 @@ def calltarget : Operand { let MIOperandInfo = (ops u18imm:$calldest); } -// Relative call target +// PC relative call target def relcalltarget : Operand { let PrintMethod = "printPCRelativeOperand"; let MIOperandInfo = (ops s16imm:$calldest); @@ -586,6 +586,11 @@ def brtarget : Operand { let PrintMethod = "printPCRelativeOperand"; } +// Hint for branch target +def hbrtarget : Operand { + let PrintMethod = "printHBROperand"; +} + // Indirect call target def indcalltarget : Operand { let PrintMethod = "printCallOperand"; diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index 48b85832e58..217da2c9ff4 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -18,6 +18,8 @@ #include "llvm/Module.h" #include "llvm/PassManager.h" #include "llvm/Target/TargetMachineRegistry.h" +#include "llvm/CodeGen/RegAllocRegistry.h" +#include "llvm/CodeGen/SchedulerRegistry.h" using namespace llvm; diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h index fa72a0adcf9..1396ff257d2 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.h +++ b/lib/Target/CellSPU/SPUTargetMachine.h @@ -83,8 +83,8 @@ public: } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/); + virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/, raw_ostream &Out); };