From aeeabb506aea5967b3ec0091c25928e49652d5fd Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 12 Nov 2018 15:20:14 +0000 Subject: [PATCH] [VectorUtils] add funnel-shifts to the list of vectorizable intrinsics This just identifies the intrinsics as candidates for vectorization. It does not mean we will attempt to vectorize under normal conditions (the test file is forcing vectorization). The cost model must be fixed to show that the transform is profitable in general. Allowing vectorization with these intrinsics is required to avoid potential regressions from canonicalizing to the intrinsics from generic IR: https://bugs.llvm.org/show_bug.cgi?id=37417 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346661 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Analysis/VectorUtils.cpp | 2 ++ test/Transforms/LoopVectorize/intrinsic.ll | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/Analysis/VectorUtils.cpp b/lib/Analysis/VectorUtils.cpp index 2fab03c988b..2cf4baf7af6 100644 --- a/lib/Analysis/VectorUtils.cpp +++ b/lib/Analysis/VectorUtils.cpp @@ -47,6 +47,8 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) { case Intrinsic::ctpop: case Intrinsic::ctlz: case Intrinsic::cttz: + case Intrinsic::fshl: + case Intrinsic::fshr: case Intrinsic::sqrt: // Begin floating-point. case Intrinsic::sin: case Intrinsic::cos: diff --git a/test/Transforms/LoopVectorize/intrinsic.ll b/test/Transforms/LoopVectorize/intrinsic.ll index b0ad22198a0..50cdb73ae8e 100644 --- a/test/Transforms/LoopVectorize/intrinsic.ll +++ b/test/Transforms/LoopVectorize/intrinsic.ll @@ -1196,7 +1196,7 @@ declare i32 @llvm.fshl.i32 (i32, i32, i32) define void @fshl_i32(i32 %n, i32* noalias %x, i32* noalias %y, i32 %shAmt) { ; CHECK-LABEL: @fshl_i32( -; CHECK-NOT: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]], <4 x i32> [[SPLAT:%.*]]) +; CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]], <4 x i32> [[SPLAT:%.*]]) ; CHECK: ret void entry: %cmp = icmp sgt i32 %n, 0 @@ -1222,7 +1222,7 @@ declare i32 @llvm.fshr.i32 (i32, i32, i32) define void @fshr_i32(i32 %n, i32* noalias %x, i32* noalias %y, i32 %shAmt) { ; CHECK-LABEL: @fshr_i32( -; CHECK-NOT: call <4 x i32> @llvm.fshr.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]], <4 x i32> [[SPLAT:%.*]]) +; CHECK: call <4 x i32> @llvm.fshr.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]], <4 x i32> [[SPLAT:%.*]]) ; CHECK: ret void entry: %cmp = icmp sgt i32 %n, 0