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ARM VFP optional data type on VMOV GPR<-->SPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1240,10 +1240,18 @@ def : VFP2InstAlias<"vsub${p}.f64 $Dn, $Dm",
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def : VFP2InstAlias<"vsub${p}.f32 $Sn, $Sm",
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(VSUBS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
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// VMOV can accept optional .f32/.f64 suffix.
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def : VFP2InstAlias<"vmov${p}.f32 $Rt, $Sn",
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// VMOV can accept optional 32-bit or less data type suffix suffix.
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def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
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(VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
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def : VFP2InstAlias<"vmov${p}.f32 $Sn, $Rt",
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def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
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(VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
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def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
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(VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
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def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
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(VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
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def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
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(VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
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def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
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(VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
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def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
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@ -271,3 +271,31 @@
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@ CHECK: vmovne s25, s26, r2, r5
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vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c]
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@ VMOV w/ optional data type suffix.
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vmov.32 s1, r8
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vmov.s16 s2, r4
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vmov.16 s3, r6
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vmov.u32 s4, r1
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vmov.p8 s5, r2
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vmov.8 s6, r3
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vmov.32 r1, s8
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vmov.s16 r2, s4
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vmov.16 r3, s6
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vmov.u32 r4, s1
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vmov.p8 r5, s2
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vmov.8 r6, s3
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@ CHECK: vmov s1, r8 @ encoding: [0x90,0x8a,0x00,0xee]
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@ CHECK: vmov s2, r4 @ encoding: [0x10,0x4a,0x01,0xee]
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@ CHECK: vmov s3, r6 @ encoding: [0x90,0x6a,0x01,0xee]
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@ CHECK: vmov s4, r1 @ encoding: [0x10,0x1a,0x02,0xee]
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@ CHECK: vmov s5, r2 @ encoding: [0x90,0x2a,0x02,0xee]
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@ CHECK: vmov s6, r3 @ encoding: [0x10,0x3a,0x03,0xee]
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@ CHECK: vmov r1, s8 @ encoding: [0x10,0x1a,0x14,0xee]
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@ CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee]
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@ CHECK: vmov r3, s6 @ encoding: [0x10,0x3a,0x13,0xee]
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@ CHECK: vmov r4, s1 @ encoding: [0x90,0x4a,0x10,0xee]
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@ CHECK: vmov r5, s2 @ encoding: [0x10,0x5a,0x11,0xee]
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@ CHECK: vmov r6, s3 @ encoding: [0x90,0x6a,0x11,0xee]
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