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[x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199808 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Woodhouse 2014-01-22 15:08:49 +00:00
parent 51cd16cbd5
commit af588b9f0e
6 changed files with 35 additions and 22 deletions
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20
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -2345,16 +2345,16 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
}
}
// Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
if (Name.startswith("outs") && Operands.size() == 3 &&
(Name == "outsb" || Name == "outsw" || Name == "outsl")) {
X86Operand &Op = *(X86Operand*)Operands.begin()[1];
X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
Operands.pop_back();
Operands.pop_back();
delete &Op;
delete &Op2;
// Append default arguments to "outs[bwld]"
if (Name.startswith("outs") && Operands.size() == 1 &&
(Name == "outsb" || Name == "outsw" || Name == "outsl" ||
Name == "outsd" )) {
if (isParsingIntelSyntax()) {
Operands.push_back(DefaultMemSIOperand(NameLoc));
Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
} else {
Operands.push_back(DefaultMemSIOperand(NameLoc));
Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
}
}

9
lib/Target/X86/X86InstrInfo.td
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@ -1772,9 +1772,12 @@ def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
}
let SchedRW = [WriteSystem] in {
def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
def OUTSL : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>, OpSize16;
def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
"outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
"outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize;
def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
"outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
}
// Flag instructions

10
test/MC/X86/index-operations.s
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@ -129,3 +129,13 @@ movsl %gs:(%esi), (%edi)
// 64: movsl %gs:(%esi), %es:(%edi) # encoding: [0x65,0x67,0xa5]
// 32: movsl %gs:(%esi), %es:(%edi) # encoding: [0x65,0xa5]
// 16: movsl %gs:(%esi), %es:(%edi) # encoding: [0x66,0x65,0x67,0xa5]
outsb
// 64: outsb (%rsi), %dx # encoding: [0x6e]
// 32: outsb (%esi), %dx # encoding: [0x6e]
// 16: outsb (%si), %dx # encoding: [0x6e]
outsw %fs:(%esi), %dx
// 64: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x67,0x6f]
// 32: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x6f]
// 16: outsw %fs:(%esi), %dx # encoding: [0x64,0x67,0x6f]

6
test/MC/X86/x86-16.s
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@ -789,21 +789,21 @@ pshufw $90, %mm4, %mm0
// CHECK: encoding: [0xe0,A]
loopnz 0
// CHECK: outsb # encoding: [0x6e]
// CHECK: outsb (%si), %dx # encoding: [0x6e]
// CHECK: outsb
// CHECK: outsb
outsb
outsb %ds:(%si), %dx
outsb (%si), %dx
// CHECK: outsw # encoding: [0x6f]
// CHECK: outsw (%si), %dx # encoding: [0x6f]
// CHECK: outsw
// CHECK: outsw
outsw
outsw %ds:(%si), %dx
outsw (%si), %dx
// CHECK: outsl # encoding: [0x66,0x6f]
// CHECK: outsl (%si), %dx # encoding: [0x66,0x6f]
// CHECK: outsl
outsl
outsl %ds:(%si), %dx

6
test/MC/X86/x86-32.s
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@ -865,21 +865,21 @@ pshufw $90, %mm4, %mm0
// CHECK: encoding: [0xe0,A]
loopnz 0
// CHECK: outsb # encoding: [0x6e]
// CHECK: outsb (%esi), %dx # encoding: [0x6e]
// CHECK: outsb
// CHECK: outsb
outsb
outsb %ds:(%esi), %dx
outsb (%esi), %dx
// CHECK: outsw # encoding: [0x66,0x6f]
// CHECK: outsw (%esi), %dx # encoding: [0x66,0x6f]
// CHECK: outsw
// CHECK: outsw
outsw
outsw %ds:(%esi), %dx
outsw (%esi), %dx
// CHECK: outsl # encoding: [0x6f]
// CHECK: outsl (%esi), %dx # encoding: [0x6f]
// CHECK: outsl
outsl
outsl %ds:(%esi), %dx

6
test/MC/X86/x86-64.s
View File

@ -1050,21 +1050,21 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1]
// CHECK: encoding: [0xe0,A]
loopnz 0
// CHECK: outsb # encoding: [0x6e]
// CHECK: outsb (%rsi), %dx # encoding: [0x6e]
// CHECK: outsb
// CHECK: outsb
outsb
outsb %ds:(%rsi), %dx
outsb (%rsi), %dx
// CHECK: outsw # encoding: [0x66,0x6f]
// CHECK: outsw (%rsi), %dx # encoding: [0x66,0x6f]
// CHECK: outsw
// CHECK: outsw
outsw
outsw %ds:(%rsi), %dx
outsw (%rsi), %dx
// CHECK: outsl # encoding: [0x6f]
// CHECK: outsl (%rsi), %dx # encoding: [0x6f]
// CHECK: outsl
outsl
outsl %ds:(%rsi), %dx