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When we use the BLEND instruction that uses the MSB as a mask, we can remove

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the VSRI instruction before it since it does not affect the MSB.

Thanks Craig Topper for suggesting this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169638 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2012-12-07 21:43:11 +00:00
parent 829c8bd98d
commit af59e9adbd
3 changed files with 8 additions and 3 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
View File

@ -15675,6 +15675,11 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
DebugLoc DL = N->getDebugLoc(); DebugLoc DL = N->getDebugLoc();
// We are going to replace the AND, OR, NAND with either BLEND
// or PSIGN, which only look at the MSB. The VSRAI instruction
// does not affect the highest bit, so we can get rid of it.
Mask = Mask.getOperand(0);
// Now we know we at least have a plendvb with the mask val. See if // Now we know we at least have a plendvb with the mask val. See if
// we can form a psignb/w/d. // we can form a psignb/w/d.
// psign = x.type == y.type == mask.type && y = sub(0, x); // psign = x.type == y.type == mask.type && y = sub(0, x);
@ -15683,7 +15688,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
"Unsupported VT for PSIGN"); "Unsupported VT for PSIGN");
Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask);
return DAG.getNode(ISD::BITCAST, DL, VT, Mask); return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
} }
// PBLENDVB only available on SSE 4.1 // PBLENDVB only available on SSE 4.1

2
test/CodeGen/X86/2011-12-28-vselecti8.ll
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@ -5,7 +5,7 @@ target triple = "x86_64-apple-darwin11.2.0"
; CHECK: @foo8 ; CHECK: @foo8
; CHECK: psll ; CHECK: psll
; CHECK: psraw ; CHECK-NOT: psraw
; CHECK: pblendvb ; CHECK: pblendvb
; CHECK: ret ; CHECK: ret
define void @foo8(float* nocapture %RET) nounwind { define void @foo8(float* nocapture %RET) nounwind {

2
test/CodeGen/X86/blend-msb.ll
View File

@ -28,7 +28,7 @@ define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
; reduce the mask in this case. ; reduce the mask in this case.
;CHECK: vsel_8xi16 ;CHECK: vsel_8xi16
;CHECK: psllw ;CHECK: psllw
;CHECK: psraw ;CHECK-NOT: psraw
;CHECK: pblendvb ;CHECK: pblendvb
;CHECK: ret ;CHECK: ret
define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) { define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {