mirror of
https://github.com/RPCS3/llvm.git
synced 2024-11-24 04:09:47 +00:00
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
added a layer of indirection with no value (not even conciseness). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143727 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
b052728368
commit
b0d9ce567f
@ -184,10 +184,6 @@ endif( ${CMAKE_SYSTEM_NAME} MATCHES SunOS )
|
||||
include(AddLLVM)
|
||||
include(TableGen)
|
||||
|
||||
macro(llvm_tablegen)
|
||||
tablegen(LLVM ${ARGN})
|
||||
endmacro()
|
||||
|
||||
if( MINGW )
|
||||
# People report that -O3 is unreliable on MinGW. The traditional
|
||||
# build also uses -O2 for that reason:
|
||||
|
@ -1,6 +1,6 @@
|
||||
set(LLVM_TARGET_DEFINITIONS Intrinsics.td)
|
||||
|
||||
llvm_tablegen(Intrinsics.gen -gen-intrinsic)
|
||||
tablegen(LLVM Intrinsics.gen -gen-intrinsic)
|
||||
|
||||
add_custom_target(intrinsics_gen ALL
|
||||
DEPENDS ${llvm_builded_incs_dir}/Intrinsics.gen)
|
||||
|
@ -1,18 +1,18 @@
|
||||
set(LLVM_TARGET_DEFINITIONS ARM.td)
|
||||
|
||||
llvm_tablegen(ARMGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(ARMGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(ARMGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
llvm_tablegen(ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
|
||||
llvm_tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
|
||||
llvm_tablegen(ARMGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(ARMGenFastISel.inc -gen-fast-isel)
|
||||
llvm_tablegen(ARMGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
llvm_tablegen(ARMGenDisassemblerTables.inc -gen-disassembler)
|
||||
tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM ARMGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
|
||||
tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
|
||||
tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
|
||||
tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM ARMGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
|
||||
add_public_tablegen_target(ARMCommonTableGen)
|
||||
|
||||
add_llvm_target(ARMCodeGen
|
||||
|
@ -1,12 +1,12 @@
|
||||
set(LLVM_TARGET_DEFINITIONS SPU.td)
|
||||
|
||||
llvm_tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(SPUGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(SPUGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(SPUGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(SPUGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(SPUGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM SPUGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM SPUGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(LLVM SPUGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM SPUGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM SPUGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM SPUGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM SPUGenCallingConv.inc -gen-callingconv)
|
||||
add_public_tablegen_target(CellSPUCommonTableGen)
|
||||
|
||||
add_llvm_target(CellSPUCodeGen
|
||||
|
@ -1,15 +1,15 @@
|
||||
set(LLVM_TARGET_DEFINITIONS MBlaze.td)
|
||||
|
||||
llvm_tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(MBlazeGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
|
||||
llvm_tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
|
||||
llvm_tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
tablegen(LLVM MBlazeGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM MBlazeGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM MBlazeGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(LLVM MBlazeGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM MBlazeGenAsmMatcher.inc -gen-asm-matcher)
|
||||
tablegen(LLVM MBlazeGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM MBlazeGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM MBlazeGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
|
||||
tablegen(LLVM MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
add_public_tablegen_target(MBlazeCommonTableGen)
|
||||
|
||||
add_llvm_target(MBlazeCodeGen
|
||||
|
@ -1,11 +1,11 @@
|
||||
set(LLVM_TARGET_DEFINITIONS MSP430.td)
|
||||
|
||||
llvm_tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(MSP430GenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM MSP430GenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM MSP430GenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM MSP430GenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM MSP430GenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM MSP430GenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM MSP430GenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(MSP430CommonTableGen)
|
||||
|
||||
add_llvm_target(MSP430CodeGen
|
||||
|
@ -1,12 +1,12 @@
|
||||
set(LLVM_TARGET_DEFINITIONS Mips.td)
|
||||
|
||||
llvm_tablegen(MipsGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(MipsGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(MipsGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(MipsGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(MipsGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(MipsCommonTableGen)
|
||||
|
||||
add_llvm_target(MipsCodeGen
|
||||
|
@ -1,10 +1,10 @@
|
||||
set(LLVM_TARGET_DEFINITIONS PTX.td)
|
||||
|
||||
llvm_tablegen(PTXGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(PTXGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(PTXGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(PTXGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM PTXGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM PTXGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM PTXGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM PTXGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM PTXGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(PTXCommonTableGen)
|
||||
|
||||
add_llvm_target(PTXCodeGen
|
||||
|
@ -1,13 +1,13 @@
|
||||
set(LLVM_TARGET_DEFINITIONS PPC.td)
|
||||
|
||||
llvm_tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(PPCGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
llvm_tablegen(PPCGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(PPCGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(PPCGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(PPCGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM PPCGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(PowerPCCommonTableGen)
|
||||
|
||||
add_llvm_target(PowerPCCodeGen
|
||||
|
@ -1,11 +1,11 @@
|
||||
set(LLVM_TARGET_DEFINITIONS Sparc.td)
|
||||
|
||||
llvm_tablegen(SparcGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(SparcGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(SparcGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(SparcGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
|
||||
add_public_tablegen_target(SparcCommonTableGen)
|
||||
|
||||
add_llvm_target(SparcCodeGen
|
||||
|
@ -1,16 +1,16 @@
|
||||
set(LLVM_TARGET_DEFINITIONS X86.td)
|
||||
|
||||
llvm_tablegen(X86GenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
|
||||
llvm_tablegen(X86GenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(X86GenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
|
||||
llvm_tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
|
||||
llvm_tablegen(X86GenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(X86GenFastISel.inc -gen-fast-isel)
|
||||
llvm_tablegen(X86GenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM X86GenDisassemblerTables.inc -gen-disassembler)
|
||||
tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM X86GenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
|
||||
tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher)
|
||||
tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
|
||||
tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM X86GenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
add_public_tablegen_target(X86CommonTableGen)
|
||||
|
||||
set(sources
|
||||
|
@ -1,11 +1,11 @@
|
||||
set(LLVM_TARGET_DEFINITIONS XCore.td)
|
||||
|
||||
llvm_tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(XCoreGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(XCoreCommonTableGen)
|
||||
|
||||
add_llvm_target(XCoreCodeGen
|
||||
|
Loading…
Reference in New Issue
Block a user