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Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190397 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Medic 2013-09-10 09:50:01 +00:00
parent 798cdc6af1
commit b15da6dc09
2 changed files with 8 additions and 0 deletions
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4
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -1404,6 +1404,10 @@ MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
RegNum = matchFPURegisterName(RegName);
if (RegKind == MipsOperand::Kind_AFGR64Regs)
RegNum /= 2;
else if (RegKind == MipsOperand::Kind_FGRH32Regs
&& !isFP64())
if (RegNum != -1 && RegNum %2 != 0)
Warning(S, "Float register should be even.");
break;
case MipsOperand::Kind_FCCRegs:
RegNum = matchFCCRegisterName(RegName);

4
test/MC/Mips/mips-fpu-instructions.s
View File

@ -167,6 +167,8 @@
# CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c]
# CHECK: lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d]
# CHECK: swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e]
# CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44]
# CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
cfc1 $a2,$0
ctc1 $10,$31
@ -196,3 +198,5 @@
suxc1 $f4, $t8($a1)
lwxc1 $f20, $12($14)
swxc1 $f26, $s2($s6)
mfhc1 $17, $f4
mthc1 $17, $f6