From b1934cd1092244d2ebb36a70a67c18b0438703a8 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Thu, 16 May 2019 13:56:23 +0000 Subject: [PATCH] [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV This is in preparation for emitting CFI directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360897 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/RISCV/atomic-cmpxchg.ll | 80 ++++++------ test/CodeGen/RISCV/atomic-rmw.ll | 120 +++++++++--------- test/CodeGen/RISCV/callee-saved-fpr32s.ll | 4 +- test/CodeGen/RISCV/callee-saved-fpr64s.ll | 4 +- test/CodeGen/RISCV/callee-saved-gprs.ll | 4 +- test/CodeGen/RISCV/fixups-relax-diff.ll | 2 +- test/CodeGen/RISCV/interrupt-attr-nocall.ll | 12 +- test/CodeGen/RISCV/interrupt-attr.ll | 8 +- .../RISCV/umulo-128-legalisation-lowering.ll | 4 +- 9 files changed, 119 insertions(+), 119 deletions(-) diff --git a/test/CodeGen/RISCV/atomic-cmpxchg.ll b/test/CodeGen/RISCV/atomic-cmpxchg.ll index c1113cdfb4d..a4526b7f46e 100644 --- a/test/CodeGen/RISCV/atomic-cmpxchg.ll +++ b/test/CodeGen/RISCV/atomic-cmpxchg.ll @@ -8,7 +8,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s -define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -86,7 +86,7 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_acquire_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -164,7 +164,7 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_acquire_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -242,7 +242,7 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_release_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -320,7 +320,7 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_release_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -398,7 +398,7 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -476,7 +476,7 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -554,7 +554,7 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -632,7 +632,7 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -710,7 +710,7 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) { +define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -788,7 +788,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) { ret void } -define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -868,7 +868,7 @@ define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_acquire_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -948,7 +948,7 @@ define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_acquire_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1028,7 +1028,7 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_release_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1108,7 +1108,7 @@ define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_release_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1188,7 +1188,7 @@ define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1268,7 +1268,7 @@ define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1348,7 +1348,7 @@ define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1428,7 +1428,7 @@ define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1508,7 +1508,7 @@ define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) { +define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind { ; RV32I-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1588,7 +1588,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) { ret void } -define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1640,7 +1640,7 @@ define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_acquire_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1692,7 +1692,7 @@ define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_acquire_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1744,7 +1744,7 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_release_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1796,7 +1796,7 @@ define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_release_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1848,7 +1848,7 @@ define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1900,7 +1900,7 @@ define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1952,7 +1952,7 @@ define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2004,7 +2004,7 @@ define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2056,7 +2056,7 @@ define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) { +define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind { ; RV32I-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2108,7 +2108,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) { ret void } -define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2168,7 +2168,7 @@ define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_acquire_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2228,7 +2228,7 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_acquire_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2288,7 +2288,7 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_release_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2348,7 +2348,7 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_release_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2408,7 +2408,7 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2468,7 +2468,7 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2528,7 +2528,7 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2588,7 +2588,7 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -2648,7 +2648,7 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) { ret void } -define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) { +define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind { ; RV32I-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 diff --git a/test/CodeGen/RISCV/atomic-rmw.ll b/test/CodeGen/RISCV/atomic-rmw.ll index c464fa61538..7fcf8b0b4ef 100644 --- a/test/CodeGen/RISCV/atomic-rmw.ll +++ b/test/CodeGen/RISCV/atomic-rmw.ll @@ -8,7 +8,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s -define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) { +define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i8_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -74,7 +74,7 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) { +define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i8_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -140,7 +140,7 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) { +define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i8_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -206,7 +206,7 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) { +define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -272,7 +272,7 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) { +define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -668,7 +668,7 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { ret i8 %1 } -define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) { +define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i8_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -734,7 +734,7 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) { +define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i8_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -800,7 +800,7 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) { +define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i8_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -866,7 +866,7 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) { +define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -932,7 +932,7 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) { +define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1268,7 +1268,7 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { ret i8 %1 } -define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) { +define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i8_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1336,7 +1336,7 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) { +define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i8_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1404,7 +1404,7 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) { +define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i8_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1472,7 +1472,7 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) { +define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1540,7 +1540,7 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) { ret i8 %1 } -define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) { +define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -4928,7 +4928,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { ret i8 %1 } -define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) { +define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -4996,7 +4996,7 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) { +define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i16_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -5064,7 +5064,7 @@ define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) { +define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i16_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -5132,7 +5132,7 @@ define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) { +define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -5200,7 +5200,7 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) { +define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -5608,7 +5608,7 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { ret i16 %1 } -define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) { +define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i16_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -5676,7 +5676,7 @@ define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) { +define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i16_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -5744,7 +5744,7 @@ define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) { +define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i16_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -5812,7 +5812,7 @@ define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) { +define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -5880,7 +5880,7 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) { +define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -6228,7 +6228,7 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { ret i16 %1 } -define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) { +define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i16_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -6298,7 +6298,7 @@ define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) { +define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i16_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -6368,7 +6368,7 @@ define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) { +define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i16_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -6438,7 +6438,7 @@ define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) { +define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -6508,7 +6508,7 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) { ret i16 %1 } -define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) { +define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10058,7 +10058,7 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { ret i16 %1 } -define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) { +define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i32_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10092,7 +10092,7 @@ define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) { +define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i32_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10126,7 +10126,7 @@ define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) { +define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i32_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10160,7 +10160,7 @@ define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) { +define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10194,7 +10194,7 @@ define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) { +define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10398,7 +10398,7 @@ define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind { ret i32 %1 } -define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) { +define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i32_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10434,7 +10434,7 @@ define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) { +define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i32_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10470,7 +10470,7 @@ define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) { +define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i32_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10506,7 +10506,7 @@ define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) { +define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i32_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10542,7 +10542,7 @@ define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) { +define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i32_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10748,7 +10748,7 @@ define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind { ret i32 %1 } -define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) { +define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i32_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10796,7 +10796,7 @@ define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) { +define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i32_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10844,7 +10844,7 @@ define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) { +define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i32_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10892,7 +10892,7 @@ define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) { +define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i32_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -10940,7 +10940,7 @@ define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) { ret i32 %1 } -define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) { +define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i32_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13148,7 +13148,7 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { ret i32 %1 } -define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) { +define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i64_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13187,7 +13187,7 @@ define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) { +define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i64_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13226,7 +13226,7 @@ define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) { +define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i64_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13265,7 +13265,7 @@ define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) { +define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13304,7 +13304,7 @@ define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) { +define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13538,7 +13538,7 @@ define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind { ret i64 %1 } -define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) { +define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i64_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13578,7 +13578,7 @@ define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) { +define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i64_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13618,7 +13618,7 @@ define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) { +define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i64_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13658,7 +13658,7 @@ define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) { +define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i64_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13698,7 +13698,7 @@ define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) { +define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_sub_i64_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13933,7 +13933,7 @@ define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind { ret i64 %1 } -define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) { +define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i64_monotonic: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -13979,7 +13979,7 @@ define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) { +define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i64_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -14025,7 +14025,7 @@ define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) { +define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i64_release: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -14071,7 +14071,7 @@ define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) { +define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i64_acq_rel: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -14117,7 +14117,7 @@ define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) { ret i64 %1 } -define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) { +define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind { ; RV32I-LABEL: atomicrmw_nand_i64_seq_cst: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 diff --git a/test/CodeGen/RISCV/callee-saved-fpr32s.ll b/test/CodeGen/RISCV/callee-saved-fpr32s.ll index f40faf59b7a..ac1f4dafeb4 100644 --- a/test/CodeGen/RISCV/callee-saved-fpr32s.ll +++ b/test/CodeGen/RISCV/callee-saved-fpr32s.ll @@ -19,7 +19,7 @@ ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns ; something appropriate. -define void @callee() { +define void @callee() nounwind { ; ILP32-LP64-LABEL: callee: ; ILP32-LP64: # %bb.0: ; ILP32-LP64-NEXT: lui a0, %hi(var) @@ -137,7 +137,7 @@ define void @callee() { ; codegen will use only ft0 in the body of caller. For the 'f' and 'd ABIs, ; fs0-fs11 are preserved across calls. -define void @caller() { +define void @caller() nounwind { ; ILP32-LP64-LABEL: caller: ; ILP32-LP64-NOT: ft{{[1-9][0-9]*}} ; ILP32-LP64-NOT: fs{{[0-9]+}} diff --git a/test/CodeGen/RISCV/callee-saved-fpr64s.ll b/test/CodeGen/RISCV/callee-saved-fpr64s.ll index b8b4729af7f..cc51b10fee1 100644 --- a/test/CodeGen/RISCV/callee-saved-fpr64s.ll +++ b/test/CodeGen/RISCV/callee-saved-fpr64s.ll @@ -15,7 +15,7 @@ ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns ; something appropriate. -define void @callee() { +define void @callee() nounwind { ; ILP32-LP64-LABEL: callee: ; ILP32-LP64: # %bb.0: ; ILP32-LP64-NEXT: lui a0, %hi(var) @@ -115,7 +115,7 @@ define void @callee() { ; codegen will use only ft0 in the body of caller. For the 'f' and 'd ABIs, ; fs0-fs11 are preserved across calls. -define void @caller() { +define void @caller() nounwind { ; ILP32-LP64-LABEL: caller: ; ILP32-LP64-NOT: ft{{[1-9][0-9]*}} ; ILP32-LP64-NOT: fs{{[0-9]+}} diff --git a/test/CodeGen/RISCV/callee-saved-gprs.ll b/test/CodeGen/RISCV/callee-saved-gprs.ll index e8b83151885..9bc7c55a909 100644 --- a/test/CodeGen/RISCV/callee-saved-gprs.ll +++ b/test/CodeGen/RISCV/callee-saved-gprs.ll @@ -24,7 +24,7 @@ ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns ; something appropriate. -define void @callee() { +define void @callee() nounwind { ; RV32I-LABEL: callee: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -80 @@ -108,7 +108,7 @@ define void @callee() { ; This function tests that RISCVRegisterInfo::getCallPreservedMask returns ; something appropriate. -define void @caller() { +define void @caller() nounwind { ; RV32I-LABEL: caller: ; RV32I: lui a0, %hi(var) ; RV32I-NEXT: addi s1, a0, %lo(var) diff --git a/test/CodeGen/RISCV/fixups-relax-diff.ll b/test/CodeGen/RISCV/fixups-relax-diff.ll index d574a8af338..e52c960b915 100644 --- a/test/CodeGen/RISCV/fixups-relax-diff.ll +++ b/test/CodeGen/RISCV/fixups-relax-diff.ll @@ -8,7 +8,7 @@ ; as the assembler takes a different path through LLVM, which is ; already covered by the fixups-expr.s test. -define i32 @main() { +define i32 @main() nounwind { entry: %retval = alloca i32, align 4 store i32 0, i32* %retval, align 4 diff --git a/test/CodeGen/RISCV/interrupt-attr-nocall.ll b/test/CodeGen/RISCV/interrupt-attr-nocall.ll index b8f6100cdd6..3e14b7511fe 100644 --- a/test/CodeGen/RISCV/interrupt-attr-nocall.ll +++ b/test/CodeGen/RISCV/interrupt-attr-nocall.ll @@ -22,7 +22,7 @@ @b = external global i32 @c = external global i32 -define void @foo_i32() #0 { +define void @foo_i32() nounwind #0 { ; CHECK-RV32-LABEL: foo_i32: ; CHECK-RV32: # %bb.0: ; CHECK-RV32-NEXT: addi sp, sp, -16 @@ -51,7 +51,7 @@ define void @foo_i32() #0 { ; Additionally check frame pointer and return address are properly saved. ; -define void @foo_fp_i32() #1 { +define void @foo_fp_i32() nounwind #1 { ; CHECK-RV32-LABEL: foo_fp_i32: ; CHECK-RV32: # %bb.0: ; CHECK-RV32-NEXT: addi sp, sp, -16 @@ -85,7 +85,7 @@ define void @foo_fp_i32() #1 { @f = external global float @d = external global float -define void @foo_float() #0 { +define void @foo_float() nounwind #0 { ; CHECK-RV32-F-LABEL: foo_float: ; CHECK-RV32-F: # %bb.0: ; CHECK-RV32-F-NEXT: addi sp, sp, -16 @@ -115,7 +115,7 @@ define void @foo_float() #0 { ; ; Additionally check frame pointer and return address are properly saved. ; -define void @foo_fp_float() #1 { +define void @foo_fp_float() nounwind #1 { ; CHECK-RV32-F-LABEL: foo_fp_float: ; CHECK-RV32-F: # %bb.0: ; CHECK-RV32-F-NEXT: addi sp, sp, -32 @@ -151,7 +151,7 @@ define void @foo_fp_float() #1 { @i = external global double @g = external global double -define void @foo_double() #0 { +define void @foo_double() nounwind #0 { ; CHECK-RV32-FD-LABEL: foo_double: ; CHECK-RV32-FD: # %bb.0: ; CHECK-RV32-FD-NEXT: addi sp, sp, -32 @@ -181,7 +181,7 @@ define void @foo_double() #0 { ; ; Additionally check frame pointer and return address are properly saved. ; -define void @foo_fp_double() #1 { +define void @foo_fp_double() nounwind #1 { ; CHECK-RV32-FD-LABEL: foo_fp_double: ; CHECK-RV32-FD: # %bb.0: ; CHECK-RV32-FD-NEXT: addi sp, sp, -32 diff --git a/test/CodeGen/RISCV/interrupt-attr.ll b/test/CodeGen/RISCV/interrupt-attr.ll index f01eec0acfd..f7831edac21 100644 --- a/test/CodeGen/RISCV/interrupt-attr.ll +++ b/test/CodeGen/RISCV/interrupt-attr.ll @@ -1060,7 +1060,7 @@ define void @foo_fp_with_call() #3 { ret void } -attributes #0 = { "interrupt"="user" } -attributes #1 = { "interrupt"="supervisor" } -attributes #2 = { "interrupt"="machine" } -attributes #3 = { "interrupt"="machine" "no-frame-pointer-elim"="true" } +attributes #0 = { nounwind "interrupt"="user" } +attributes #1 = { nounwind "interrupt"="supervisor" } +attributes #2 = { nounwind "interrupt"="machine" } +attributes #3 = { nounwind "interrupt"="machine" "no-frame-pointer-elim"="true" } diff --git a/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll b/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll index b45afb979fa..e0ac6483a5d 100644 --- a/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll +++ b/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32 -define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 { +define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 { ; RISCV32-LABEL: muloti_test: ; RISCV32: # %bb.0: # %start ; RISCV32-NEXT: addi sp, sp, -80 @@ -123,6 +123,6 @@ start: ; Function Attrs: nounwind readnone speculatable declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1 -attributes #0 = { nounwind readnone uwtable } +attributes #0 = { nounwind readnone } attributes #1 = { nounwind readnone speculatable } attributes #2 = { nounwind }