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Make sure FABS on v2f32 and v4f32 is legal on ARM NEON
This fixes PR14359 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -505,7 +505,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
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setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
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setOperationAction(ISD::FABS, MVT::v4f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
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setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
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setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
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@ -4877,12 +4877,15 @@ defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
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defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
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IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
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int_arm_neon_vabs>;
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def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
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IIC_VUNAD, "vabs", "f32",
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v2f32, v2f32, int_arm_neon_vabs>;
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def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
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IIC_VUNAQ, "vabs", "f32",
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v4f32, v4f32, int_arm_neon_vabs>;
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def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
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"vabs", "f32",
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v2f32, v2f32, fabs>;
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def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
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"vabs", "f32",
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v4f32, v4f32, fabs>;
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def : Pat<(v2f32 (int_arm_neon_vabs (v2f32 DPR:$src))), (VABSfd DPR:$src)>;
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def : Pat<(v4f32 (int_arm_neon_vabs (v4f32 QPR:$src))), (VABSfq QPR:$src)>;
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// VQABS : Vector Saturating Absolute Value
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defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
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17
test/CodeGen/ARM/fabs-neon.ll
Normal file
17
test/CodeGen/ARM/fabs-neon.ll
Normal file
@ -0,0 +1,17 @@
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; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s
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; CHECK: test:
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; CHECK: vabs.f32 q0, q0
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define <4 x float> @test(<4 x float> %a) {
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%foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
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ret <4 x float> %foo
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}
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declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
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; CHECK: test2:
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; CHECK: vabs.f32 d0, d0
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define <2 x float> @test2(<2 x float> %a) {
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%foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
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ret <2 x float> %foo
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}
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declare <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
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