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[MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs()
Apparently, MachineInstr class definition as well as pretty much all of the machine passes assume that the only kind of MachineInstr's operands that is variadic for variadic opcodes is explicit non-definitions. In particular, this assumption is made by MachineInstr::defs(), uses(), and explicit_uses() methods, as well as by MachineCSE pass. The assumption is incorrect judging from at least TableGen backend implementation, that recognizes variable_ops in OutOperandList, and the very existence of G_UNMERGE_VALUES generic opcode, or ARM load multiple instructions, all of which have variadic defs. In particular, MachineCSE pass breaks MIR with CSE'able G_UNMERGE_VALUES instructions in it. This commit implements MachineInstr::getNumExplicitDefs() similar to pre-existing MachineInstr::getNumExplicitOperands(), fixes MachineInstr::defs(), uses(), and explicit_uses(), and fixes MachineCSE pass. As the issue addressed seems to affect only machine passes that could be ran mid-GlobalISel pipeline at the moment, the other passes aren't fixed by this commit, like MachineLICM: that could be done on per-pass basis when (if ever) they get adopted for GlobalISel. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D45640 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334520 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Roman Tereshin
parent
299cf5ff6a
commit
b1c42dee78
@ -322,6 +322,11 @@ public:
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return Operands[i];
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}
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/// Returns the total number of definitions.
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unsigned getNumDefs() const {
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return getNumExplicitDefs() + MCID->getNumImplicitDefs();
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}
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/// Return true if operand \p OpIdx is a subregister index.
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bool isOperandSubregIdx(unsigned OpIdx) const {
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assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
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@ -340,6 +345,9 @@ public:
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/// Returns the number of non-implicit operands.
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unsigned getNumExplicitOperands() const;
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/// Returns the number of non-implicit definitions.
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unsigned getNumExplicitDefs() const;
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/// iterator/begin/end - Iterate over all operands of a machine instruction.
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using mop_iterator = MachineOperand *;
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using const_mop_iterator = const MachineOperand *;
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@ -374,31 +382,29 @@ public:
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/// Implicit definition are not included!
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iterator_range<mop_iterator> defs() {
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return make_range(operands_begin(),
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operands_begin() + getDesc().getNumDefs());
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operands_begin() + getNumExplicitDefs());
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}
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/// \copydoc defs()
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iterator_range<const_mop_iterator> defs() const {
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return make_range(operands_begin(),
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operands_begin() + getDesc().getNumDefs());
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operands_begin() + getNumExplicitDefs());
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}
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/// Returns a range that includes all operands that are register uses.
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/// This may include unrelated operands which are not register uses.
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iterator_range<mop_iterator> uses() {
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return make_range(operands_begin() + getDesc().getNumDefs(),
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operands_end());
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return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
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}
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/// \copydoc uses()
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iterator_range<const_mop_iterator> uses() const {
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return make_range(operands_begin() + getDesc().getNumDefs(),
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operands_end());
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return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
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}
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iterator_range<mop_iterator> explicit_uses() {
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return make_range(operands_begin() + getDesc().getNumDefs(),
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operands_begin() + getNumExplicitOperands() );
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return make_range(operands_begin() + getNumExplicitDefs(),
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operands_begin() + getNumExplicitOperands());
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}
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iterator_range<const_mop_iterator> explicit_uses() const {
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return make_range(operands_begin() + getDesc().getNumDefs(),
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operands_begin() + getNumExplicitOperands() );
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return make_range(operands_begin() + getNumExplicitDefs(),
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operands_begin() + getNumExplicitOperands());
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}
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/// Returns the number of the operand iterator \p I points to.
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@ -550,8 +550,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
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// Check if it's profitable to perform this CSE.
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bool DoCSE = true;
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unsigned NumDefs = MI->getDesc().getNumDefs() +
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MI->getDesc().getNumImplicitDefs();
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unsigned NumDefs = MI->getNumDefs();
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for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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@ -519,21 +519,39 @@ void MachineInstr::eraseFromBundle() {
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getParent()->erase_instr(this);
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}
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/// getNumExplicitOperands - Returns the number of non-implicit operands.
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///
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unsigned MachineInstr::getNumExplicitOperands() const {
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unsigned NumOperands = MCID->getNumOperands();
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if (!MCID->isVariadic())
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return NumOperands;
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for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = getOperand(i);
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if (!MO.isReg() || !MO.isImplicit())
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NumOperands++;
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for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = getOperand(I);
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// The operands must always be in the following order:
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// - explicit reg defs,
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// - other explicit operands (reg uses, immediates, etc.),
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// - implicit reg defs
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// - implicit reg uses
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if (MO.isReg() && MO.isImplicit())
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break;
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++NumOperands;
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}
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return NumOperands;
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}
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unsigned MachineInstr::getNumExplicitDefs() const {
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unsigned NumDefs = MCID->getNumDefs();
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if (!MCID->isVariadic())
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return NumDefs;
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for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = getOperand(I);
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if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
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break;
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++NumDefs;
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}
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return NumDefs;
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}
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void MachineInstr::bundleWithPred() {
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assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
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setFlag(BundledPred);
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@ -179,3 +179,102 @@ body: |
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$w0 = COPY %4
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RET_ReallyLR implicit $w0
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...
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---
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name: variadic_defs_unmerge_vector
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legalized: true
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regBankSelected: false
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selected: false
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body: |
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; CHECK-LABEL: name: variadic_defs_unmerge_vector
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
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; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)
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; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
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; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
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; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
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; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]
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; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
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; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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bb.0:
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%0 :_(<4 x s16>) = COPY $d0
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%1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
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%5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
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%9 :_(s16), %10:_(s16), %11:_(s16), %12:_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
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%13:_(s16), %14:_(s16), %15:_(s16), %16:_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
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%17:_(s32) = G_ANYEXT %1 (s16)
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%18:_(s32) = G_ANYEXT %6 (s16)
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%19:_(s32) = G_ANYEXT %11(s16)
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%20:_(s32) = G_ANYEXT %16(s16)
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%21:_(s32) = G_ADD %17, %18
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%22:_(s32) = G_ADD %19, %20
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%23:_(s32) = G_ADD %21, %22
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$w0 = COPY %23(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: variadic_defs_unmerge_scalar
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legalized: true
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regBankSelected: false
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selected: false
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body: |
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; CHECK-LABEL: name: variadic_defs_unmerge_scalar
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)
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; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
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; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
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; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
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; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]
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; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
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; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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bb.0:
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%0 :_(s64) = COPY $d0
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%1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(s64)
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%5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(s64)
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%9 :_(s16), %10:_(s16), %11:_(s16), %12:_(s16) = G_UNMERGE_VALUES %0(s64)
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%13:_(s16), %14:_(s16), %15:_(s16), %16:_(s16) = G_UNMERGE_VALUES %0(s64)
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%17:_(s32) = G_ANYEXT %1 (s16)
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%18:_(s32) = G_ANYEXT %6 (s16)
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%19:_(s32) = G_ANYEXT %11(s16)
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%20:_(s32) = G_ANYEXT %16(s16)
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%21:_(s32) = G_ADD %17, %18
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%22:_(s32) = G_ADD %19, %20
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%23:_(s32) = G_ADD %21, %22
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$w0 = COPY %23(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: variadic_defs_unmerge_scalar_asym
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legalized: true
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regBankSelected: false
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selected: false
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body: |
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; CHECK-LABEL: name: variadic_defs_unmerge_scalar_asym
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[UV01:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)
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; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
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; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV01]], [[UV23]]
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; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
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; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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bb.0:
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%0 :_(s64) = COPY $d0
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%1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(s64)
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%9 :_(s32), %10:_(s32) = G_UNMERGE_VALUES %0(s64)
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%5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(s64)
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%11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %0(s64)
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%17:_(s32) = G_ANYEXT %1 (s16)
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%18:_(s32) = G_ANYEXT %6 (s16)
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%21:_(s32) = G_ADD %17, %18
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%22:_(s32) = G_ADD %9, %12
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%23:_(s32) = G_ADD %21, %22
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$w0 = COPY %23(s32)
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RET_ReallyLR implicit $w0
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...
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