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Add support for NEON VLD2-dup instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
bebfbc560b
commit
b1dfa7a8e0
@ -140,6 +140,13 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
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{ ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 },
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{ ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 },
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{ ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4},
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{ ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4},
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{ ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, SingleSpc, 2, 2},
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{ ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, SingleSpc, 2, 2},
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{ ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, SingleSpc, 2, 8},
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{ ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, SingleSpc, 2, 8},
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{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 },
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{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 },
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{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 },
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@ -933,6 +940,12 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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case ARM::VLD1DUPq8Pseudo_UPD:
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case ARM::VLD1DUPq16Pseudo_UPD:
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case ARM::VLD1DUPq32Pseudo_UPD:
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case ARM::VLD2DUPd8Pseudo:
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case ARM::VLD2DUPd16Pseudo:
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case ARM::VLD2DUPd32Pseudo:
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case ARM::VLD2DUPd8Pseudo_UPD:
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case ARM::VLD2DUPd16Pseudo_UPD:
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case ARM::VLD2DUPd32Pseudo_UPD:
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ExpandVLD(MBBI);
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break;
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@ -197,6 +197,11 @@ private:
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SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
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unsigned *DOpcodes, unsigned *QOpcodes);
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/// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
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/// should be 2, 3 or 4. The opcode array specifies the instructions used
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/// for loading D registers. (Q registers are not supported.)
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SDNode *SelectVLDDup(SDNode *N, unsigned NumVecs, unsigned *Opcodes);
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/// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
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/// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
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/// generated to force the table registers to be consecutive.
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@ -1643,6 +1648,62 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, unsigned NumVecs,
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unsigned *Opcodes) {
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assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
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DebugLoc dl = N->getDebugLoc();
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SDValue MemAddr, Align;
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if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
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return NULL;
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SDValue Chain = N->getOperand(0);
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EVT VT = N->getValueType(0);
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unsigned Alignment = 0;
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if (NumVecs != 3) {
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Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
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unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
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if (Alignment > NumBytes)
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Alignment = NumBytes;
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// Alignment must be a power of two; make sure of that.
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Alignment = (Alignment & -Alignment);
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if (Alignment == 1)
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Alignment = 0;
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}
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Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
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unsigned OpcodeIndex;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld-dup type");
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case MVT::v8i8: OpcodeIndex = 0; break;
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case MVT::v4i16: OpcodeIndex = 1; break;
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case MVT::v2f32:
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case MVT::v2i32: OpcodeIndex = 2; break;
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}
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SDValue Pred = getAL(CurDAG);
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SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
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SDValue SuperReg;
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unsigned Opc = Opcodes[OpcodeIndex];
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const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
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unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
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EVT ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
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SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
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SuperReg = SDValue(VLdDup, 0);
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Chain = SDValue(VLdDup, 1);
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// Extract the subregisters.
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assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
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unsigned SubIdx = ARM::dsub_0;
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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ReplaceUses(SDValue(N, Vec),
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CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
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ReplaceUses(SDValue(N, NumVecs), Chain);
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
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unsigned Opc) {
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assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
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@ -2294,6 +2355,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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N->getOperand(2), N->getOperand(3));
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}
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case ARMISD::VLD2DUP: {
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unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
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ARM::VLD2DUPd32Pseudo };
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return SelectVLDDup(N, 2, Opcodes);
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}
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case ISD::INTRINSIC_VOID:
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case ISD::INTRINSIC_W_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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@ -824,6 +824,9 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::BFI: return "ARMISD::BFI";
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case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
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case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
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case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
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case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
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case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
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}
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}
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@ -4836,15 +4839,100 @@ static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
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DAG.getUNDEF(VT), NewMask.data());
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}
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/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
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/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
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/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
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/// return true.
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static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
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SelectionDAG &DAG = DCI.DAG;
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EVT VT = N->getValueType(0);
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// vldN-dup instructions only support 64-bit vectors for N > 1.
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if (!VT.is64BitVector())
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return false;
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// Check if the VDUPLANE operand is a vldN-dup intrinsic.
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SDNode *VLD = N->getOperand(0).getNode();
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if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
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return false;
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unsigned NumVecs = 0;
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unsigned NewOpc = 0;
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unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
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if (IntNo == Intrinsic::arm_neon_vld2lane) {
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NumVecs = 2;
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NewOpc = ARMISD::VLD2DUP;
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} else if (IntNo == Intrinsic::arm_neon_vld3lane) {
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NumVecs = 3;
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NewOpc = ARMISD::VLD3DUP;
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} else if (IntNo == Intrinsic::arm_neon_vld4lane) {
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NumVecs = 4;
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NewOpc = ARMISD::VLD4DUP;
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} else {
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return false;
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}
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// First check that all the vldN-lane uses are VDUPLANEs and that the lane
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// numbers match the load.
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unsigned VLDLaneNo =
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cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
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for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
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UI != UE; ++UI) {
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// Ignore uses of the chain result.
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if (UI.getUse().getResNo() == NumVecs)
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continue;
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SDNode *User = *UI;
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if (User->getOpcode() != ARMISD::VDUPLANE ||
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VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
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return false;
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}
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// Create the vldN-dup node.
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EVT Tys[5];
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unsigned n;
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for (n = 0; n < NumVecs; ++n)
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Tys[n] = VT;
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Tys[n] = MVT::Other;
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SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
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SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
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MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
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SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
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Ops, 2, VLDMemInt->getMemoryVT(),
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VLDMemInt->getMemOperand());
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// Update the uses.
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for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
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UI != UE; ++UI) {
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unsigned ResNo = UI.getUse().getResNo();
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// Ignore uses of the chain result.
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if (ResNo == NumVecs)
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continue;
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SDNode *User = *UI;
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DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
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}
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// Now the vldN-lane intrinsic is dead except for its chain result.
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// Update uses of the chain.
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std::vector<SDValue> VLDDupResults;
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for (unsigned n = 0; n < NumVecs; ++n)
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VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
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VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
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DCI.CombineTo(VLD, VLDDupResults);
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return true;
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}
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/// PerformVDUPLANECombine - Target-specific dag combine xforms for
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/// ARMISD::VDUPLANE.
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static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
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// If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
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// redundant.
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static SDValue PerformVDUPLANECombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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SDValue Op = N->getOperand(0);
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EVT VT = N->getValueType(0);
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// Ignore bit_converts.
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// If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
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// of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
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if (CombineVLDDUP(N, DCI))
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return SDValue(N, 0);
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// If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
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// redundant. Ignore bit_converts for now; element sizes are checked below.
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while (Op.getOpcode() == ISD::BITCAST)
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Op = Op.getOperand(0);
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if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
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@ -4857,10 +4945,11 @@ static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
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unsigned EltBits;
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if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
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EltSize = 8;
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EVT VT = N->getValueType(0);
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if (EltSize > VT.getVectorElementType().getSizeInBits())
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return SDValue();
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return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
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return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
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}
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/// getVShiftImm - Check if this is a valid build_vector for the immediate
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@ -5248,7 +5337,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
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case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
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case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
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case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
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case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
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case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
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case ISD::SHL:
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case ISD::SRA:
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@ -172,7 +172,12 @@ namespace llvm {
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// Vector OR with immediate
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VORRIMM,
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// Vector AND with NOT of immediate
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VBICIMM
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VBICIMM,
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// Vector load N-element structure to all lanes:
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VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
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VLD3DUP,
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VLD4DUP
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};
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}
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@ -854,6 +854,47 @@ def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
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def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
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// VLD2DUP : Vector Load (single 2-element structure to all lanes)
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class VLD2DUP<bits<4> op7_4, string Dt>
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: NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
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(ins addrmode6:$Rn), IIC_VLD2dup,
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"vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{4} = Rn{4};
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}
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def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
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def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
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def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
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def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
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def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
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def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
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// ...with double-spaced registers (not used for codegen):
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def VLD2DUPd8Q : VLD2DUP<{0,0,1,?}, "8">;
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def VLD2DUPd16Q : VLD2DUP<{0,1,1,?}, "16">;
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def VLD2DUPd32Q : VLD2DUP<{1,0,1,?}, "32">;
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// ...with address register writeback:
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class VLD2DUPWB<bits<4> op7_4, string Dt>
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: NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2dupu,
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"vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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}
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def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
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def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
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def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
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def VLD2DUPd8Q_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
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def VLD2DUPd16Q_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
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def VLD2DUPd32Q_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
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def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
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def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
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def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
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// VLD3DUP : Vector Load (single 3-element structure to all lanes)
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// VLD4DUP : Vector Load (single 4-element structure to all lanes)
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// FIXME: Not yet implemented.
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@ -146,6 +146,8 @@ def IIC_VLD2u : InstrItinClass;
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def IIC_VLD2x2u : InstrItinClass;
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def IIC_VLD2ln : InstrItinClass;
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def IIC_VLD2lnu : InstrItinClass;
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def IIC_VLD2dup : InstrItinClass;
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def IIC_VLD2dupu : InstrItinClass;
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def IIC_VLD3 : InstrItinClass;
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def IIC_VLD3ln : InstrItinClass;
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def IIC_VLD3u : InstrItinClass;
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@ -523,6 +523,18 @@ def CortexA8Itineraries : ProcessorItineraries<
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InstrStage<3, [A8_LSPipe]>],
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[3, 3, 2, 1, 1, 1, 1, 1]>,
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//
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// VLD2dup
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InstrItinData<IIC_VLD2dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<2, [A8_NLSPipe], 0>,
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InstrStage<2, [A8_LSPipe]>],
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[2, 1]>,
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//
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// VLD2dupu
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InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<2, [A8_NLSPipe], 0>,
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InstrStage<2, [A8_LSPipe]>],
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[2, 2, 1, 1]>,
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//
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// VLD3
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InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrStage<4, [A8_NLSPipe], 0>,
|
||||
|
||||
@ -887,6 +887,24 @@ def CortexA9Itineraries : ProcessorItineraries<
|
||||
InstrStage<3, [A9_LSUnit]>],
|
||||
[4, 4, 2, 1, 1, 1, 1, 1]>,
|
||||
//
|
||||
// VLD2dup
|
||||
InstrItinData<IIC_VLD2dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<2, [A9_NPipe], 0>,
|
||||
InstrStage<2, [A9_LSUnit]>],
|
||||
[3, 1]>,
|
||||
//
|
||||
// VLD2dupu
|
||||
InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<2, [A9_NPipe], 0>,
|
||||
InstrStage<2, [A9_LSUnit]>],
|
||||
[3, 2, 1, 1]>,
|
||||
//
|
||||
// VLD3
|
||||
InstrItinData<IIC_VLD3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
|
||||
@ -39,3 +39,35 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
|
||||
%tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <16 x i32> zeroinitializer
|
||||
ret <16 x i8> %tmp3
|
||||
}
|
||||
|
||||
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
|
||||
%struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }
|
||||
|
||||
define <8 x i8> @vld2dupi8(i8* %A) nounwind {
|
||||
;CHECK: vld2dupi8:
|
||||
;Check the (default) alignment value.
|
||||
;CHECK: vld2.8 {d16[], d17[]}, [r0]
|
||||
%tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
|
||||
%tmp1 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 0
|
||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
|
||||
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 1
|
||||
%tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> undef, <8 x i32> zeroinitializer
|
||||
%tmp5 = add <8 x i8> %tmp2, %tmp4
|
||||
ret <8 x i8> %tmp5
|
||||
}
|
||||
|
||||
define <2 x i32> @vld2dupi32(i32* %A) nounwind {
|
||||
;CHECK: vld2dupi32:
|
||||
;Check the alignment value. Max for this instruction is 64 bits:
|
||||
;CHECK: vld2.32 {d16[], d17[]}, [r0, :64]
|
||||
%tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i32* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
|
||||
%tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0
|
||||
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
|
||||
%tmp3 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 1
|
||||
%tmp4 = shufflevector <2 x i32> %tmp3, <2 x i32> undef, <2 x i32> zeroinitializer
|
||||
%tmp5 = add <2 x i32> %tmp2, %tmp4
|
||||
ret <2 x i32> %tmp5
|
||||
}
|
||||
|
||||
declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
|
||||
declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i32*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
|
||||
|
||||
Loading…
Reference in New Issue
Block a user