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TargetInstrInfo::hasOperandInterlock() is always true, because it is

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never overridden by any target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-07-28 19:24:48 +00:00
parent 8b88d906a2
commit b2f30a3792
3 changed files with 4 additions and 29 deletions
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11
include/llvm/Target/TargetInstrInfo.h
View File

@ -194,18 +194,11 @@ public:
bool isDummyPhiInstr(MachineOpCode opCode) const { bool isDummyPhiInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_DUMMY_PHI_FLAG; return get(opCode).Flags & M_DUMMY_PHI_FLAG;
} }
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued
// before the results are ready.
// Default to true since most instructions on many architectures allow this.
//
virtual bool hasOperandInterlock(MachineOpCode opCode) const {
return true;
}
virtual bool hasResultInterlock(MachineOpCode opCode) const { virtual bool hasResultInterlock(MachineOpCode opCode) const {
return true; return true;
} }
// //
// Latencies for individual instructions and instruction pairs // Latencies for individual instructions and instruction pairs
// //

11
lib/CodeGen/InstrSched/InstrScheduling.cpp
View File

@ -1045,11 +1045,6 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep) && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
return false; return false;
// for now, don't put an instruction that does not have operand
// interlocks in the delay slot of a branch
if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
return false;
// Finally, if the instruction precedes the branch, we make sure the // Finally, if the instruction precedes the branch, we make sure the
// instruction can be reordered relative to the branch. We simply check // instruction can be reordered relative to the branch. We simply check
// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
@ -1326,11 +1321,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
const SchedGraphNode* dnode = delayNodeVec[i]; const SchedGraphNode* dnode = delayNodeVec[i];
if ( ! S.isScheduled(dnode) if ( ! S.isScheduled(dnode)
&& S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot) && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
&& instrIsFeasible(S, dnode->getOpcode())) && instrIsFeasible(S, dnode->getOpcode())) {
{
assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
&& "Instructions without interlocks not yet supported "
"when filling branch delay slots");
S.scheduleInstr(dnode, nextSlot, nextTime); S.scheduleInstr(dnode, nextSlot, nextTime);
break; break;
} }

11
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
View File

@ -1045,11 +1045,6 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep) && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
return false; return false;
// for now, don't put an instruction that does not have operand
// interlocks in the delay slot of a branch
if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
return false;
// Finally, if the instruction precedes the branch, we make sure the // Finally, if the instruction precedes the branch, we make sure the
// instruction can be reordered relative to the branch. We simply check // instruction can be reordered relative to the branch. We simply check
// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
@ -1326,11 +1321,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
const SchedGraphNode* dnode = delayNodeVec[i]; const SchedGraphNode* dnode = delayNodeVec[i];
if ( ! S.isScheduled(dnode) if ( ! S.isScheduled(dnode)
&& S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot) && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
&& instrIsFeasible(S, dnode->getOpcode())) && instrIsFeasible(S, dnode->getOpcode())) {
{
assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
&& "Instructions without interlocks not yet supported "
"when filling branch delay slots");
S.scheduleInstr(dnode, nextSlot, nextTime); S.scheduleInstr(dnode, nextSlot, nextTime);
break; break;
} }