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Also replace uses of SRL if that's also folded during ReduceLoadWidth().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2279,6 +2279,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
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unsigned EVTBits = MVT::getSizeInBits(EVT);
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unsigned ShAmt = 0;
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bool CombineSRL = false;
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if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
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if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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ShAmt = N01->getValue();
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@ -2288,6 +2289,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
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if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
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return SDOperand();
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ShAmt /= 8;
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CombineSRL = true;
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}
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}
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}
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@ -2317,7 +2319,12 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
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: DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
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LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
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AddToWorkList(N);
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CombineTo(N0.Val, Load, Load.getValue(1));
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if (CombineSRL) {
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std::vector<SDNode*> NowDead;
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DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
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CombineTo(N->getOperand(0).Val, Load);
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} else
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CombineTo(N0.Val, Load, Load.getValue(1));
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if (ShAmt)
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return DAG.getNode(N->getOpcode(), VT, Load);
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return SDOperand(N, 0); // Return N so it doesn't get rechecked!
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