diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 0891adc0e30..5b1b77b2d56 100644
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -200,6 +200,16 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
                          Addr, Base, Disp, Index);
   }
 
+  // Return an undefined i64 value.
+  SDValue getUNDEF64(SDLoc DL);
+
+  // Convert N to VT, if it isn't already.
+  SDValue convertTo(SDLoc DL, EVT VT, SDValue N);
+
+  // Try to use RISBG to implement ISD::AND node N.  Return the selected
+  // node on success, otherwise return null.
+  SDNode *tryRISBGForAND(SDNode *N);
+
   // If Op0 is null, then Node is a constant that can be loaded using:
   //
   //   (Opcode UpperVal LowerVal)
@@ -521,6 +531,107 @@ bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form,
   return true;
 }
 
+// Return true if Mask matches the regexp 0*1+0*, given that zero masks
+// have already been filtered out.  Store the first set bit in LSB and
+// the number of set bits in Length if so.
+static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
+  unsigned First = findFirstSet(Mask);
+  uint64_t Top = (Mask >> First) + 1;
+  if ((Top & -Top) == Top)
+    {
+      LSB = First;
+      Length = findFirstSet(Top);
+      return true;
+    }
+  return false;
+}
+
+// Return a mask with Count low bits set.
+static uint64_t allOnes(unsigned int Count) {
+  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
+}
+
+// Return true if RISBG can be used to extract the bits in Mask from
+// a value that has BitSize bits.  Store the start and end operands
+// (I3 and I4) in Start and End if so.
+static bool isRISBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start,
+                        unsigned &End) {
+  // Reject trivial all-zero and all-one masks.
+  uint64_t Used = allOnes(BitSize);
+  if (Mask == 0 || Mask == Used)
+    return false;
+
+  // Handle the 1+0+ or 0+1+0* cases.  Start then specifies the index of
+  // the msb and End specifies the index of the lsb.
+  unsigned LSB, Length;
+  if (isStringOfOnes(Mask, LSB, Length))
+    {
+      Start = 63 - (LSB + Length - 1);
+      End = 63 - LSB;
+      return true;
+    }
+
+  // Handle the wrap-around 1+0+1+ cases.  Start then specifies the msb
+  // of the low 1s and End specifies the lsb of the high 1s.
+  if (isStringOfOnes(Mask ^ Used, LSB, Length))
+    {
+      assert(LSB > 0 && "Bottom bit must be set");
+      assert(LSB + Length < BitSize && "Top bit must be set");
+      Start = 63 - (LSB - 1);
+      End = 63 - (LSB + Length);
+      return true;
+    }
+
+  return false;
+}
+
+SDValue SystemZDAGToDAGISel::getUNDEF64(SDLoc DL) {
+  SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64);
+  return SDValue(N, 0);
+}
+
+SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) {
+  if (N.getValueType() == MVT::i32 && VT == MVT::i64) {
+    SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
+    SDNode *Insert = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG,
+                                            DL, VT, getUNDEF64(DL), N, Index);
+    return SDValue(Insert, 0);
+  }
+  if (N.getValueType() == MVT::i64 && VT == MVT::i32) {
+    SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
+    SDNode *Extract = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
+                                             DL, VT, N, Index);
+    return SDValue(Extract, 0);
+  }
+  assert(N.getValueType() == VT && "Unexpected value types");
+  return N;
+}
+
+SDNode *SystemZDAGToDAGISel::tryRISBGForAND(SDNode *N) {
+  EVT VT = N->getValueType(0);
+  unsigned BitSize = VT.getSizeInBits();
+  unsigned Start, End;
+  ConstantSDNode *MaskNode =
+    dyn_cast<ConstantSDNode>(N->getOperand(1).getNode());
+  if (!MaskNode
+      || !isRISBGMask(MaskNode->getZExtValue(), BitSize, Start, End))
+    return 0;
+
+  // Prefer register extensions like LLC over RSIBG.
+  if ((Start == 32 || Start == 48 || Start == 56) && End == 63)
+    return 0;
+
+  SDValue Ops[5] = {
+    getUNDEF64(SDLoc(N)),
+    convertTo(SDLoc(N), MVT::i64, N->getOperand(0)),
+    CurDAG->getTargetConstant(Start, MVT::i32),
+    CurDAG->getTargetConstant(End | 128, MVT::i32),
+    CurDAG->getTargetConstant(0, MVT::i32)
+  };
+  N = CurDAG->getMachineNode(SystemZ::RISBG, SDLoc(N), MVT::i64, Ops);
+  return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
+}
+
 SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
                                                  SDValue Op0, uint64_t UpperVal,
                                                  uint64_t LowerVal) {
@@ -590,6 +701,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
   }
 
   unsigned Opcode = Node->getOpcode();
+  SDNode *ResNode = 0;
   switch (Opcode) {
   case ISD::OR:
   case ISD::XOR:
@@ -604,6 +716,10 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
       }
     break;
 
+  case ISD::AND:
+    ResNode = tryRISBGForAND(Node);
+    break;
+
   case ISD::Constant:
     // If this is a 64-bit constant that is out of the range of LLILF,
     // LLIHF and LGFI, split it into two 32-bit pieces.
@@ -631,7 +747,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
   }
 
   // Select the default instruction
-  SDNode *ResNode = SelectCode(Node);
+  if (!ResNode)
+    ResNode = SelectCode(Node);
 
   DEBUG(errs() << "=> ";
         if (ResNode == NULL || ResNode == Node)
diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll
index c125ffa71a7..bf2ad7bda9c 100644
--- a/test/CodeGen/SystemZ/addr-01.ll
+++ b/test/CodeGen/SystemZ/addr-01.ll
@@ -65,8 +65,8 @@ define void @f5(i64 %addr, i64 %index) {
 ; An address with an index and a displacement added using OR.
 define void @f6(i64 %addr, i64 %index) {
 ; CHECK: f6:
-; CHECK: nill %r2, 65528
-; CHECK: lb %r0, 6(%r3,%r2)
+; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
+; CHECK: lb %r0, 6(%r3,[[BASE]])
 ; CHECK: br %r14
   %aligned = and i64 %addr, -8
   %or = or i64 %aligned, 6
@@ -93,10 +93,10 @@ define void @f7(i64 %addr, i64 %index) {
 ; about the alignment of %add here.
 define void @f8(i64 %addr, i64 %index) {
 ; CHECK: f8:
-; CHECK: nill %r2, 65528
-; CHECK: agr %r2, %r3
-; CHECK: oill %r2, 6
-; CHECK: lb %r0, 0(%r2)
+; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
+; CHECK: agr [[BASE]], %r3
+; CHECK: oill [[BASE]], 6
+; CHECK: lb %r0, 0([[BASE]])
 ; CHECK: br %r14
   %aligned = and i64 %addr, -8
   %add = add i64 %aligned, %index
diff --git a/test/CodeGen/SystemZ/addr-02.ll b/test/CodeGen/SystemZ/addr-02.ll
index 6772c1d4180..6e5c92f3a1a 100644
--- a/test/CodeGen/SystemZ/addr-02.ll
+++ b/test/CodeGen/SystemZ/addr-02.ll
@@ -71,8 +71,8 @@ define void @f5(i64 %addr, i64 %index, i8 **%dst) {
 ; An address with an index and a displacement added using OR.
 define void @f6(i64 %addr, i64 %index, i8 **%dst) {
 ; CHECK: f6:
-; CHECK: nill %r2, 65528
-; CHECK: lb %r0, 6(%r3,%r2)
+; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
+; CHECK: lb %r0, 6(%r3,[[BASE]])
 ; CHECK: br %r14
   %aligned = and i64 %addr, -8
   %or = or i64 %aligned, 6
@@ -101,10 +101,10 @@ define void @f7(i64 %addr, i64 %index, i8 **%dst) {
 ; about the alignment of %add here.
 define void @f8(i64 %addr, i64 %index, i8 **%dst) {
 ; CHECK: f8:
-; CHECK: nill %r2, 65528
-; CHECK: agr %r2, %r3
-; CHECK: oill %r2, 6
-; CHECK: lb %r0, 0(%r2)
+; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
+; CHECK: agr [[BASE]], %r3
+; CHECK: oill [[BASE]], 6
+; CHECK: lb %r0, 0([[BASE]])
 ; CHECK: br %r14
   %aligned = and i64 %addr, -8
   %add = add i64 %aligned, %index
diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll
index 1852c913505..df14e27f1ea 100644
--- a/test/CodeGen/SystemZ/alloca-01.ll
+++ b/test/CodeGen/SystemZ/alloca-01.ll
@@ -1,8 +1,7 @@
 ; Test variable-sized allocas and addresses based on them in cases where
 ; stack arguments are needed.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK1
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK2
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C
@@ -15,34 +14,19 @@ declare i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 %f, i64 %g)
 ; There are two stack arguments, so an offset of 160 + 2 * 8 == 176
 ; is added to the copy of %r15.
 define i64 @f1(i64 %length, i64 %index) {
-; The full allocation sequence is:
-;
-;    la %r0, 7(%r2)      1
-;    nill %r0, 0xfff8    1
-;    lgr %r1, %r15         2
-;    sgr %r1, %r0        1 2
-;    lgr %r15, %r1         2
-;
-; The third instruction does not depend on the first two, so check for
-; two fully-ordered sequences.
-;
 ; FIXME: a better sequence would be:
 ;
 ;    lgr %r1, %r15
 ;    sgr %r1, %r2
-;    nill %r1, 0xfff8
+;    risbg %r1, %r1, 0, 188, 0
 ;    lgr %r15, %r1
 ;
-; CHECK1: f1:
-; CHECK1: la %r0, 7(%r2)
-; CHECK1: nill %r0, 65528
-; CHECK1: sgr %r1, %r0
-; CHECK1: lgr %r15, %r1
-;
-; CHECK2: f1:
-; CHECK2: lgr %r1, %r15
-; CHECK2: sgr %r1, %r0
-; CHECK2: lgr %r15, %r1
+; CHECK: f1:
+; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
+; CHECK-DAG: risbg [[REG2:%r[0-5]]], [[REG1]], 0, 188, 0
+; CHECK-DAG: lgr [[REG3:%r[0-5]]], %r15
+; CHECK: sgr [[REG3]], [[REG2]]
+; CHECK: lgr %r15, [[REG3]]
 ;
 ; CHECK-A: f1:
 ; CHECK-A: lgr %r15, %r1
diff --git a/test/CodeGen/SystemZ/and-02.ll b/test/CodeGen/SystemZ/and-02.ll
index a0fff81492a..152c1b84fbc 100644
--- a/test/CodeGen/SystemZ/and-02.ll
+++ b/test/CodeGen/SystemZ/and-02.ll
@@ -2,91 +2,227 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-; Check the lowest useful NILF value.
+; ANDs with 1 should use RISBG
 define i32 @f1(i32 %a) {
 ; CHECK: f1:
-; CHECK: nilf %r2, 1
+; CHECK: risbg %r2, %r2, 63, 191, 0
 ; CHECK: br %r14
   %and = and i32 %a, 1
   ret i32 %and
 }
 
-; Check the highest 16-bit constant that must be handled by NILF.
+; ...same for 2.
 define i32 @f2(i32 %a) {
 ; CHECK: f2:
-; CHECK: nilf %r2, 65534
+; CHECK: risbg %r2, %r2, 62, 190, 0
 ; CHECK: br %r14
-  %and = and i32 %a, 65534
+  %and = and i32 %a, 2
+  ret i32 %and
+}
+
+; ...and 3.
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: risbg %r2, %r2, 62, 191, 0
+; CHECK: br %r14
+  %and = and i32 %a, 3
+  ret i32 %and
+}
+
+; ...and 4.
+define i32 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: risbg %r2, %r2, 61, 189, 0
+; CHECK: br %r14
+  %and = and i32 %a, 4
+  ret i32 %and
+}
+
+; Check the lowest useful NILF value.
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: nilf %r2, 5
+; CHECK: br %r14
+  %and = and i32 %a, 5
+  ret i32 %and
+}
+
+; Check the highest 16-bit constant that must be handled by NILF.
+define i32 @f6(i32 %a) {
+; CHECK: f6:
+; CHECK: nilf %r2, 65533
+; CHECK: br %r14
+  %and = and i32 %a, 65533
   ret i32 %and
 }
 
 ; ANDs of 0xffff are zero extensions from i16.
-define i32 @f3(i32 %a) {
-; CHECK: f3:
+define i32 @f7(i32 %a) {
+; CHECK: f7:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %and = and i32 %a, 65535
   ret i32 %and
 }
 
-; Check the next value up, which must again use NILF.
-define i32 @f4(i32 %a) {
-; CHECK: f4:
-; CHECK: nilf %r2, 65536
+; Check the next value up, which can use RISBG.
+define i32 @f8(i32 %a) {
+; CHECK: f8:
+; CHECK: risbg %r2, %r2, 47, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, 65536
   ret i32 %and
 }
 
-; Check the lowest useful NILH value.  (LLHR is used instead of NILH of 0.)
-define i32 @f5(i32 %a) {
-; CHECK: f5:
-; CHECK: nilh %r2, 1
+; Check the next value up, which must again use NILF.
+define i32 @f9(i32 %a) {
+; CHECK: f9:
+; CHECK: nilf %r2, 65537
+; CHECK: br %r14
+  %and = and i32 %a, 65537
+  ret i32 %and
+}
+
+; This value is in range of NILH, but we use RISBG instead.
+define i32 @f10(i32 %a) {
+; CHECK: f10:
+; CHECK: risbg %r2, %r2, 47, 191, 0
 ; CHECK: br %r14
   %and = and i32 %a, 131071
   ret i32 %and
 }
 
+; Check the lowest useful NILH value.
+define i32 @f11(i32 %a) {
+; CHECK: f11:
+; CHECK: nilh %r2, 2
+; CHECK: br %r14
+  %and = and i32 %a, 196607
+  ret i32 %and
+}
+
+; Check the highest useful NILH value.
+define i32 @f12(i32 %a) {
+; CHECK: f12:
+; CHECK: nilh %r2, 65530
+; CHECK: br %r14
+  %and = and i32 %a, -327681
+  ret i32 %and
+}
+
+; Check the equivalent of NILH of 65531, which can use RISBG.
+define i32 @f13(i32 %a) {
+; CHECK: f13:
+; CHECK: risbg %r2, %r2, 46, 172, 0
+; CHECK: br %r14
+  %and = and i32 %a, -262145
+  ret i32 %and
+}
+
+; ...same for 65532.
+define i32 @f14(i32 %a) {
+; CHECK: f14:
+; CHECK: risbg %r2, %r2, 48, 173, 0
+; CHECK: br %r14
+  %and = and i32 %a, -196609
+  ret i32 %and
+}
+
+; ...and 65533.
+define i32 @f15(i32 %a) {
+; CHECK: f15:
+; CHECK: risbg %r2, %r2, 47, 173, 0
+; CHECK: br %r14
+  %and = and i32 %a, -131073
+  ret i32 %and
+}
+
 ; Check the highest useful NILF value.
-define i32 @f6(i32 %a) {
-; CHECK: f6:
+define i32 @f16(i32 %a) {
+; CHECK: f16:
 ; CHECK: nilf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i32 %a, -65538
   ret i32 %and
 }
 
-; Check the highest useful NILH value, which is one up from the above.
-define i32 @f7(i32 %a) {
-; CHECK: f7:
-; CHECK: nilh %r2, 65534
+; Check the next value up, which is the equivalent of an NILH of 65534.
+; We use RISBG instead.
+define i32 @f17(i32 %a) {
+; CHECK: f17:
+; CHECK: risbg %r2, %r2, 48, 174, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65537
   ret i32 %and
 }
 
-; Check the low end of the NILL range, which is one up again.
-define i32 @f8(i32 %a) {
-; CHECK: f8:
-; CHECK: nill %r2, 0
+; Check the next value up, which can also use RISBG.
+define i32 @f18(i32 %a) {
+; CHECK: f18:
+; CHECK: risbg %r2, %r2, 32, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65536
   ret i32 %and
 }
 
-; Check the next value up.
-define i32 @f9(i32 %a) {
-; CHECK: f9:
-; CHECK: nill %r2, 1
+; ...and again.
+define i32 @f19(i32 %a) {
+; CHECK: f19:
+; CHECK: risbg %r2, %r2, 63, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65535
   ret i32 %and
 }
 
+; Check the next value up again, which is the lowest useful NILL value.
+define i32 @f20(i32 %a) {
+; CHECK: f20:
+; CHECK: nill %r2, 2
+; CHECK: br %r14
+  %and = and i32 %a, -65534
+  ret i32 %and
+}
+
 ; Check the highest useful NILL value.
-define i32 @f10(i32 %a) {
-; CHECK: f10:
-; CHECK: nill %r2, 65534
+define i32 @f21(i32 %a) {
+; CHECK: f21:
+; CHECK: nill %r2, 65530
+; CHECK: br %r14
+  %and = and i32 %a, -6
+  ret i32 %and
+}
+
+; Check the next value up, which can use RISBG.
+define i32 @f22(i32 %a) {
+; CHECK: f22:
+; CHECK: risbg %r2, %r2, 62, 188, 0
+; CHECK: br %r14
+  %and = and i32 %a, -5
+  ret i32 %and
+}
+
+; ...and again.
+define i32 @f23(i32 %a) {
+; CHECK: f23:
+; CHECK: risbg %r2, %r2, 32, 189, 0
+; CHECK: br %r14
+  %and = and i32 %a, -4
+  ret i32 %and
+}
+
+; ...and again.
+define i32 @f24(i32 %a) {
+; CHECK: f24:
+; CHECK: risbg %r2, %r2, 63, 189, 0
+; CHECK: br %r14
+  %and = and i32 %a, -3
+  ret i32 %and
+}
+
+; Check the last useful mask.
+define i32 @f25(i32 %a) {
+; CHECK: f25:
+; CHECK: risbg %r2, %r2, 32, 190, 0
 ; CHECK: br %r14
   %and = and i32 %a, -2
   ret i32 %and
diff --git a/test/CodeGen/SystemZ/and-04.ll b/test/CodeGen/SystemZ/and-04.ll
index 62def60026e..e94def69159 100644
--- a/test/CodeGen/SystemZ/and-04.ll
+++ b/test/CodeGen/SystemZ/and-04.ll
@@ -2,13 +2,10 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-; There is no 64-bit AND instruction for a mask of 1.
-; FIXME: we ought to be able to require "ngr %r2, %r0", but at the moment,
-; two-address optimisations force "ngr %r0, %r2; lgr %r2, %r0" instead.
+; Use RISBG for a single bit.
 define i64 @f1(i64 %a) {
 ; CHECK: f1:
-; CHECK: lghi %r0, 1
-; CHECK: ngr
+; CHECK: risbg %r2, %r2, 63, 191, 0
 ; CHECK: br %r14
   %and = and i64 %a, 1
   ret i64 %and
@@ -17,8 +14,7 @@ define i64 @f1(i64 %a) {
 ; Likewise 0xfffe.
 define i64 @f2(i64 %a) {
 ; CHECK: f2:
-; CHECK: llill %r0, 65534
-; CHECK: ngr
+; CHECK: risbg %r2, %r2, 48, 190, 0
 ; CHECK: br %r14
   %and = and i64 %a, 65534
   ret i64 %and
@@ -33,21 +29,19 @@ define i64 @f3(i64 %a) {
   ret i64 %and
 }
 
-; Check the next value up, which again has no dedicated instruction.
+; Check the next value up, which can again use RISBG.
 define i64 @f4(i64 %a) {
 ; CHECK: f4:
-; CHECK: llilh %r0, 1
-; CHECK: ngr
+; CHECK: risbg %r2, %r2, 47, 175, 0
 ; CHECK: br %r14
   %and = and i64 %a, 65536
   ret i64 %and
 }
 
-; Check 0xfffffffe.
+; Check 0xfffffffe, which can also use RISBG.
 define i64 @f5(i64 %a) {
 ; CHECK: f5:
-; CHECK: lilf %r0, 4294967294
-; CHECK: ngr
+; CHECK: risbg %r2, %r2, 32, 190, 0
 ; CHECK: br %r14
   %and = and i64 %a, 4294967294
   ret i64 %and
@@ -62,30 +56,30 @@ define i64 @f6(i64 %a) {
   ret i64 %and
 }
 
-; Check the lowest useful NIHF value (0x00000001_ffffffff).
+; Check the lowest useful NIHF value (0x00000002_ffffffff).
 define i64 @f7(i64 %a) {
 ; CHECK: f7:
-; CHECK: nihf %r2, 1
+; CHECK: nihf %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, 8589934591
+  %and = and i64 %a, 12884901887
   ret i64 %and
 }
 
-; Check the low end of the NIHH range (0x0000ffff_ffffffff).
+; Check the lowest useful NIHH value (0x0002ffff_ffffffff).
 define i64 @f8(i64 %a) {
 ; CHECK: f8:
-; CHECK: nihh %r2, 0
+; CHECK: nihh %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, 281474976710655
+  %and = and i64 %a, 844424930131967
   ret i64 %and
 }
 
-; Check the highest useful NIHH value (0xfffeffff_ffffffff).
+; Check the highest useful NIHH value (0xfffaffff_ffffffff).
 define i64 @f9(i64 %a) {
 ; CHECK: f9:
-; CHECK: nihh %r2, 65534
+; CHECK: nihh %r2, 65530
 ; CHECK: br %r14
-  %and = and i64 %a, -281474976710657
+  %and = and i64 %a, -1407374883553281
   ret i64 %and
 }
 
@@ -98,83 +92,83 @@ define i64 @f10(i64 %a) {
   ret i64 %and
 }
 
-; Check the low end of the NIHL range (0xffff0000_ffffffff).
+; Check the lowest useful NIHL value (0xffff0002_ffffffff).
 define i64 @f11(i64 %a) {
 ; CHECK: f11:
-; CHECK: nihl %r2, 0
+; CHECK: nihl %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, -281470681743361
+  %and = and i64 %a, -281462091808769
   ret i64 %and
 }
 
-; Check the highest useful NIHL value (0xfffffffe_ffffffff).
+; Check the highest useful NIHL value (0xfffffffa_ffffffff).
 define i64 @f12(i64 %a) {
 ; CHECK: f12:
-; CHECK: nihl %r2, 65534
+; CHECK: nihl %r2, 65530
 ; CHECK: br %r14
-  %and = and i64 %a, -4294967297
+  %and = and i64 %a, -21474836481
   ret i64 %and
 }
 
-; Check the low end of the NILF range (0xffffffff_00000000).
+; Check the lowest useful NILF range (0xffffffff_00000002).
 define i64 @f13(i64 %a) {
 ; CHECK: f13:
-; CHECK: nilf %r2, 0
+; CHECK: nilf %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, -4294967296
+  %and = and i64 %a, -4294967294
   ret i64 %and
 }
 
-; Check the low end of the NILH range (0xffffffff_0000ffff).
+; Check the low end of the NILH range (0xffffffff_0002ffff).
 define i64 @f14(i64 %a) {
 ; CHECK: f14:
-; CHECK: nilh %r2, 0
+; CHECK: nilh %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, -4294901761
+  %and = and i64 %a, -4294770689
   ret i64 %and
 }
 
 ; Check the next value up, which must use NILF.
 define i64 @f15(i64 %a) {
 ; CHECK: f15:
-; CHECK: nilf %r2, 65536
+; CHECK: nilf %r2, 196608
 ; CHECK: br %r14
-  %and = and i64 %a, -4294901760
+  %and = and i64 %a, -4294770688
+  ret i64 %and
+}
+
+; Check the highest useful NILH value (0xffffffff_fffaffff).
+define i64 @f16(i64 %a) {
+; CHECK: f16:
+; CHECK: nilh %r2, 65530
+; CHECK: br %r14
+  %and = and i64 %a, -327681
   ret i64 %and
 }
 
 ; Check the maximum useful NILF value (0xffffffff_fffefffe).
-define i64 @f16(i64 %a) {
-; CHECK: f16:
+define i64 @f17(i64 %a) {
+; CHECK: f17:
 ; CHECK: nilf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i64 %a, -65538
   ret i64 %and
 }
 
-; Check the highest useful NILH value, which is one greater than the above.
-define i64 @f17(i64 %a) {
-; CHECK: f17:
-; CHECK: nilh %r2, 65534
-; CHECK: br %r14
-  %and = and i64 %a, -65537
-  ret i64 %and
-}
-
-; Check the low end of the NILL range, which is one greater again.
+; Check the lowest useful NILL value (0xffffffff_ffff0002).
 define i64 @f18(i64 %a) {
 ; CHECK: f18:
-; CHECK: nill %r2, 0
+; CHECK: nill %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, -65536
+  %and = and i64 %a, -65534
   ret i64 %and
 }
 
 ; Check the highest useful NILL value.
 define i64 @f19(i64 %a) {
 ; CHECK: f19:
-; CHECK: nill %r2, 65534
+; CHECK: nill %r2, 65530
 ; CHECK: br %r14
-  %and = and i64 %a, -2
+  %and = and i64 %a, -6
   ret i64 %and
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-01.ll b/test/CodeGen/SystemZ/atomicrmw-add-01.ll
index 615b2921abe..3074c548f92 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-01.ll
@@ -14,14 +14,14 @@
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: ar [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -48,14 +48,14 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-02.ll b/test/CodeGen/SystemZ/atomicrmw-add-02.ll
index 95fb02ae641..24c336b79a7 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-02.ll
@@ -14,14 +14,14 @@
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: ar [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -48,14 +48,14 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-01.ll b/test/CodeGen/SystemZ/atomicrmw-and-01.ll
index 6d66df3b50e..cd4104da83f 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-01.ll
@@ -14,14 +14,14 @@
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -49,14 +49,14 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: nilh [[ROT]], 33023
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-02.ll b/test/CodeGen/SystemZ/atomicrmw-and-02.ll
index 76e33bb3ce7..a19d18705e3 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-02.ll
@@ -14,14 +14,14 @@
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -49,14 +49,14 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: nilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
index bf490d89294..9e1e7ff71a4 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
@@ -14,16 +14,16 @@
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -50,16 +50,16 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check signed maximum.
 define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -86,9 +86,9 @@ define i8 @f2(i8 *%src, i8 %b) {
 ; Check unsigned minimum.
 define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK: f3:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: clr [[ROT]], %r3
@@ -96,7 +96,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -123,9 +123,9 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; Check unsigned maximum.
 define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK: f4:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: clr [[ROT]], %r3
@@ -133,7 +133,7 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
index b2c7bc90288..78c95df11f4 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
@@ -14,16 +14,16 @@
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -50,16 +50,16 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check signed maximum.
 define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -86,9 +86,9 @@ define i16 @f2(i16 *%src, i16 %b) {
 ; Check unsigned minimum.
 define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK: f3:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: clr [[ROT]], %r3
@@ -96,7 +96,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -123,9 +123,9 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; Check unsigned maximum.
 define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK: f4:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: clr [[ROT]], %r3
@@ -133,7 +133,7 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
index b5f2c101412..260286fe195 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
@@ -14,15 +14,15 @@
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -50,15 +50,15 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: nilh [[ROT]], 33023
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
index 7a37a38ef92..383c2e513ea 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
@@ -14,15 +14,15 @@
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -50,15 +50,15 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: nilh [[ROT]], 32768
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-01.ll b/test/CodeGen/SystemZ/atomicrmw-or-01.ll
index f0313d60c12..c63087e87f3 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-01.ll
@@ -14,14 +14,14 @@
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: or [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -48,14 +48,14 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: oilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-02.ll b/test/CodeGen/SystemZ/atomicrmw-or-02.ll
index 5c3f286996e..3b8efcb80c5 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-02.ll
@@ -14,14 +14,14 @@
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: or [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -48,14 +48,14 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: oilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
index 31cbdf5d06d..b17c36f713a 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
@@ -14,14 +14,14 @@
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: sr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -48,14 +48,14 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
index f72bf4a1221..dbacacdbd6f 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
@@ -14,14 +14,14 @@
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: sr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -48,14 +48,14 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
index 502fa2f8a03..a44eadfc464 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
@@ -12,14 +12,14 @@
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 24
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
index 55ede412588..1b6e84660d6 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
@@ -12,14 +12,14 @@
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 16
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
index 4801e80eb32..5f0957a090b 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
@@ -14,14 +14,14 @@
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: xr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
@@ -48,14 +48,14 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: xilf [[ROT]], 2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
index 7a525a89977..cdad3ef9ea3 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
@@ -14,14 +14,14 @@
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: f1:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: xr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
@@ -48,14 +48,14 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
 ; CHECK: f2:
-; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
-; CHECK: nill %r2, 65532
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
+; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
+; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
+; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: xilf [[ROT]], 2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
-; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
+; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK: jlh [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/cmpxchg-01.ll b/test/CodeGen/SystemZ/cmpxchg-01.ll
index 03fabee1328..bbb0aabb07e 100644
--- a/test/CodeGen/SystemZ/cmpxchg-01.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-01.ll
@@ -12,16 +12,16 @@
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; CHECK-MAIN: f1:
-; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3
-; CHECK-MAIN: nill %r3, 65532
-; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3)
+; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
+; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
+; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
 ; CHECK-MAIN: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK-MAIN: risbg %r4, %r2, 32, 55, 0
 ; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
 ; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0
 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
-; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
+; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK-MAIN: jlh [[LOOP]]
 ; CHECK-MAIN: [[EXIT]]:
 ; CHECK-MAIN-NOT: %r2
diff --git a/test/CodeGen/SystemZ/cmpxchg-02.ll b/test/CodeGen/SystemZ/cmpxchg-02.ll
index b5005bb291e..5f2dd3aa7d5 100644
--- a/test/CodeGen/SystemZ/cmpxchg-02.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-02.ll
@@ -12,16 +12,16 @@
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; CHECK-MAIN: f1:
-; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3
-; CHECK-MAIN: nill %r3, 65532
-; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3)
+; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
+; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
+; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
 ; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
 ; CHECK-MAIN: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK-MAIN: risbg %r4, %r2, 32, 47, 0
 ; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
 ; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0
 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}})
-; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
+; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[BASE]])
 ; CHECK-MAIN: jlh [[LOOP]]
 ; CHECK-MAIN: [[EXIT]]:
 ; CHECK-MAIN-NOT: %r2
diff --git a/test/CodeGen/SystemZ/fp-move-02.ll b/test/CodeGen/SystemZ/fp-move-02.ll
index c2bb931a939..a02c8564125 100644
--- a/test/CodeGen/SystemZ/fp-move-02.ll
+++ b/test/CodeGen/SystemZ/fp-move-02.ll
@@ -39,9 +39,9 @@ define float @f3(i64 %big) {
 define float @f4(i64 %big) {
 ; CHECK: f4:
 ; CHECK-NOT: %r2
-; CHECK: nilf %r2, 0
-; CHECK-NOT: %r2
-; CHECK: ldgr %f0, %r2
+; CHECK: risbg [[REG:%r[0-5]]], %r2, 0, 159, 0
+; CHECK-NOT: [[REG]]
+; CHECK: ldgr %f0, [[REG]]
   %shift = ashr i64 %big, 32
   %a = trunc i64 %shift to i32
   %res = bitcast i32 %a to float
diff --git a/test/CodeGen/SystemZ/insert-01.ll b/test/CodeGen/SystemZ/insert-01.ll
index 98ddf56959b..2ff9ff4bee2 100644
--- a/test/CodeGen/SystemZ/insert-01.ll
+++ b/test/CodeGen/SystemZ/insert-01.ll
@@ -33,7 +33,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) {
 ; register value.  We can use IC but must keep the original mask.
 define i32 @f3(i32 %orig, i8 *%ptr) {
 ; CHECK: f3:
-; CHECK: nill %r2, 65024
+; CHECK: risbg %r2, %r2, 32, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -46,7 +46,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) {
 ; Like f3, but with the operands reversed.
 define i32 @f4(i32 %orig, i8 *%ptr) {
 ; CHECK: f4:
-; CHECK: nill %r2, 65024
+; CHECK: risbg %r2, %r2, 32, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/insert-02.ll b/test/CodeGen/SystemZ/insert-02.ll
index 471889dede6..e9980144e9e 100644
--- a/test/CodeGen/SystemZ/insert-02.ll
+++ b/test/CodeGen/SystemZ/insert-02.ll
@@ -33,7 +33,7 @@ define i64 @f2(i64 %orig, i8 *%ptr) {
 ; register value.  We can use IC but must keep the original mask.
 define i64 @f3(i64 %orig, i8 *%ptr) {
 ; CHECK: f3:
-; CHECK: nill %r2, 65024
+; CHECK: risbg %r2, %r2, 0, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -46,7 +46,7 @@ define i64 @f3(i64 %orig, i8 *%ptr) {
 ; Like f3, but with the operands reversed.
 define i64 @f4(i64 %orig, i8 *%ptr) {
 ; CHECK: f4:
-; CHECK: nill %r2, 65024
+; CHECK: risbg %r2, %r2, 0, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
   %val = load i8 *%ptr