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The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-31 22:00:41 +00:00
parent 08c2862540
commit b45b11bce1
2 changed files with 6 additions and 5 deletions
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3
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3243,7 +3243,9 @@ class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
: T2I<oops, iops, itin, opc, asm, pattern> { : T2I<oops, iops, itin, opc, asm, pattern> {
let Inst{31-20} = op31_20{11-0}; let Inst{31-20} = op31_20{11-0};
let Inst{15-14} = op15_14{1-0}; let Inst{15-14} = op15_14{1-0};
let Inst{13} = 0b0;
let Inst{12} = op12{0}; let Inst{12} = op12{0};
let Inst{7-0} = 0;
} }
class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12, class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
@ -3276,7 +3278,6 @@ def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
bits<4> Rn; bits<4> Rn;
let Inst{19-16} = Rn; let Inst{19-16} = Rn;
let Inst{20} = mask{4}; // R Bit let Inst{20} = mask{4}; // R Bit
let Inst{13} = 0b0;
let Inst{11-8} = mask{3-0}; let Inst{11-8} = mask{3-0};
} }

8
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2603,17 +2603,17 @@ DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
unsigned pred = fieldFromInstruction32(Insn, 22, 4); unsigned pred = fieldFromInstruction32(Insn, 22, 4);
if (pred == 0xE || pred == 0xF) { if (pred == 0xE || pred == 0xF) {
unsigned opc = fieldFromInstruction32(Insn, 4, 2); unsigned opc = fieldFromInstruction32(Insn, 4, 28);
switch (opc) { switch (opc) {
default: default:
return Fail; return Fail;
case 0: case 0xf3bf8f4:
Inst.setOpcode(ARM::t2DSB); Inst.setOpcode(ARM::t2DSB);
break; break;
case 1: case 0xf3bf8f5:
Inst.setOpcode(ARM::t2DMB); Inst.setOpcode(ARM::t2DMB);
break; break;
case 2: case 0xf3bf8f6:
Inst.setOpcode(ARM::t2ISB); Inst.setOpcode(ARM::t2ISB);
return Success; return Success;
} }