RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-08 13:00:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-04-05 23:55:28 +00:00
parent 53c5e7b2e7
commit b48c791515
2 changed files with 42 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -5029,7 +5029,12 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case ARM::ADCSSrs:
case ARM::SBCSSri:
case ARM::SBCSSrr:
case ARM::SBCSSrs: {
case ARM::SBCSSrs:
case ARM::RSBSri:
case ARM::RSBSrr:
case ARM::RSBSrs:
case ARM::RSCSri:
case ARM::RSCSrs: {
unsigned OldOpc = MI->getOpcode();
unsigned Opc = 0;
switch (OldOpc) {
@ -5051,6 +5056,21 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case ARM::SBCSSrs:
Opc = ARM::SBCrs;
break;
case ARM::RSBSri:
Opc = ARM::RSBri;
break;
case ARM::RSBSrr:
Opc = ARM::RSBrr;
break;
case ARM::RSBSrs:
Opc = ARM::RSBrs;
break;
case ARM::RSCSri:
Opc = ARM::RSCri;
break;
case ARM::RSCSrs:
Opc = ARM::RSCrs;
break;
default:
llvm_unreachable("Unknown opcode?");
}

85
lib/Target/ARM/ARMInstrInfo.td
View File

@ -935,7 +935,8 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
}
}
// Carry setting variants
let isCodeGenOnly = 1, Defs = [CPSR] in {
// NOTE: CPSR def omitted because it will be handled by the custom inserter.
let usesCustomInserter = 1 in {
multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
Size4Bytes, IIC_iALUi,
@ -2243,44 +2244,17 @@ def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
}
// RSB with 's' bit set.
let isCodeGenOnly = 1, Defs = [CPSR] in {
def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
[(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
let Inst{20} = 1;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
let Inst{11-0} = imm;
}
def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{11-0} = shift;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
// NOTE: CPSR def omitted because it will be handled by the custom inserter.
let usesCustomInserter = 1 in {
def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
Size4Bytes, IIC_iALUi,
[(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
Size4Bytes, IIC_iALUr,
[/* For disassembly only; pattern left blank */]>;
def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
Size4Bytes, IIC_iALUsr,
[(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
}
let Uses = [CPSR] in {
@ -2325,33 +2299,16 @@ def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
}
// FIXME: Allow these to be predicated.
let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
// NOTE: CPSR def omitted because it will be handled by the custom inserter.
let usesCustomInserter = 1, Uses = [CPSR] in {
def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
Size4Bytes, IIC_iALUi,
[(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
Requires<[IsARM]> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
let Inst{20} = 1;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
let Inst{11-0} = imm;
}
def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
Requires<[IsARM]>;
def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
Size4Bytes, IIC_iALUsr,
[(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
Requires<[IsARM]> {
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{11-0} = shift;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
Requires<[IsARM]>;
}
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.