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Revert r261070, it caused PR26652 / PR26653.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261127 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nico Weber
parent
80a961a80c
commit
b512b02828
@ -328,7 +328,6 @@ private:
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bool NoInfs : 1;
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bool NoSignedZeros : 1;
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bool AllowReciprocal : 1;
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bool VectorReduction : 1;
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public:
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/// Default constructor turns off all optimization flags.
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@ -341,7 +340,6 @@ public:
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NoInfs = false;
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NoSignedZeros = false;
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AllowReciprocal = false;
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VectorReduction = false;
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}
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// These are mutators for each flag.
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@ -353,7 +351,6 @@ public:
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void setNoInfs(bool b) { NoInfs = b; }
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void setNoSignedZeros(bool b) { NoSignedZeros = b; }
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void setAllowReciprocal(bool b) { AllowReciprocal = b; }
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void setVectorReduction(bool b) { VectorReduction = b; }
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// These are accessors for each flag.
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bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
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@ -364,7 +361,6 @@ public:
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bool hasNoInfs() const { return NoInfs; }
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bool hasNoSignedZeros() const { return NoSignedZeros; }
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bool hasAllowReciprocal() const { return AllowReciprocal; }
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bool hasVectorReduction() const { return VectorReduction; }
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/// Return a raw encoding of the flags.
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/// This function should only be used to add data to the NodeID value.
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@ -2308,125 +2308,6 @@ void SelectionDAGBuilder::visitFSub(const User &I) {
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visitBinary(I, ISD::FSUB);
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}
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/// Checks if the given instruction performs a vector reduction, in which case
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/// we have the freedom to alter the elements in the result as long as the
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/// reduction of them stays unchanged.
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static bool isVectorReductionOp(const User *I) {
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const Instruction *Inst = dyn_cast<Instruction>(I);
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if (!Inst || !Inst->getType()->isVectorTy())
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return false;
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auto OpCode = Inst->getOpcode();
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switch (OpCode) {
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case Instruction::Add:
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case Instruction::Mul:
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case Instruction::And:
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case Instruction::Or:
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case Instruction::Xor:
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break;
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case Instruction::FAdd:
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case Instruction::FMul:
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if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
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if (FPOp->getFastMathFlags().unsafeAlgebra())
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break;
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// Fall through.
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default:
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return false;
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}
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unsigned ElemNum = Inst->getType()->getVectorNumElements();
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unsigned ElemNumToReduce = ElemNum;
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// Do DFS search on the def-use chain from the given instruction. We only
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// allow four kinds of operations during the search until we reach the
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// instruction that extracts the first element from the vector:
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//
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// 1. The reduction operation of the same opcode as the given instruction.
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//
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// 2. PHI node.
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//
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// 3. ShuffleVector instruction together with a reduction operation that
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// does a partial reduction.
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//
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// 4. ExtractElement that extracts the first element from the vector, and we
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// stop searching the def-use chain here.
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//
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// 3 & 4 above perform a reduction on all elements of the vector. We push defs
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// from 1-3 to the stack to continue the DFS. The given instruction is not
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// a reduction operation if we meet any other instructions other than those
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// listed above.
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SmallVector<const User *, 16> UsersToVisit{Inst};
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SmallPtrSet<const User *, 16> Visited;
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bool ReduxExtracted = false;
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while (!UsersToVisit.empty()) {
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auto User = UsersToVisit.back();
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UsersToVisit.pop_back();
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if (!Visited.insert(User).second)
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continue;
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for (const auto &U : User->users()) {
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auto Inst = dyn_cast<Instruction>(U);
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if (!Inst)
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return false;
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if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) {
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if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
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if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().unsafeAlgebra())
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return false;
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UsersToVisit.push_back(U);
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} else if (const ShuffleVectorInst *ShufInst =
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dyn_cast<ShuffleVectorInst>(U)) {
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// Detect the following pattern: A ShuffleVector instruction together
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// with a reduction that do partial reduction on the first and second
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// ElemNumToReduce / 2 elements, and store the result in
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// ElemNumToReduce / 2 elements in another vector.
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if (ElemNumToReduce == 1)
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return false;
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if (!isa<UndefValue>(U->getOperand(1)))
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return false;
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for (unsigned i = 0; i < ElemNumToReduce / 2; ++i)
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if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2))
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return false;
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for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i)
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if (ShufInst->getMaskValue(i) != -1)
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return false;
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// There is only one user of this ShuffleVector instruction, which must
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// be a reduction operation.
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if (!U->hasOneUse())
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return false;
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auto U2 = dyn_cast<Instruction>(*U->user_begin());
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if (!U2 || U2->getOpcode() != OpCode)
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return false;
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// Check operands of the reduction operation.
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if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) ||
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(U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) {
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UsersToVisit.push_back(U2);
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ElemNumToReduce /= 2;
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} else
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return false;
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} else if (isa<ExtractElementInst>(U)) {
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// At this moment we should have reduced all elements in the vector.
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if (ElemNumToReduce != 1)
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return false;
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const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1));
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if (!Val || Val->getZExtValue() != 0)
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return false;
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ReduxExtracted = true;
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} else
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return false;
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}
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}
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return ReduxExtracted;
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}
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void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
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SDValue Op1 = getValue(I.getOperand(0));
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SDValue Op2 = getValue(I.getOperand(1));
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@ -2434,7 +2315,6 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
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bool nuw = false;
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bool nsw = false;
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bool exact = false;
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bool vec_redux = false;
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FastMathFlags FMF;
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if (const OverflowingBinaryOperator *OFBinOp =
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@ -2448,16 +2328,10 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
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if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
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FMF = FPOp->getFastMathFlags();
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if (isVectorReductionOp(&I)) {
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vec_redux = true;
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DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n");
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}
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SDNodeFlags Flags;
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Flags.setExact(exact);
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Flags.setNoSignedWrap(nsw);
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Flags.setNoUnsignedWrap(nuw);
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Flags.setVectorReduction(vec_redux);
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if (EnableFMFInDAG) {
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Flags.setAllowReciprocal(FMF.allowReciprocal());
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Flags.setNoInfs(FMF.noInfs());
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@ -1,85 +0,0 @@
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; RUN: llc < %s -debug-only=isel -o /dev/null 2>&1 | FileCheck %s
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; REQUIRES: asserts
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@a = global [1024 x i32] zeroinitializer, align 16
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define float @reduce_add_float(float* nocapture readonly %a) {
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; CHECK-LABEL: reduce_add_float
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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; CHECK: Detected a reduction operation: {{.*}} fadd fast
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;
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entry:
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next.4, %vector.body ]
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%vec.phi = phi <4 x float> [ zeroinitializer, %entry ], [ %28, %vector.body ]
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%vec.phi9 = phi <4 x float> [ zeroinitializer, %entry ], [ %29, %vector.body ]
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%0 = getelementptr inbounds float, float* %a, i64 %index
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%1 = bitcast float* %0 to <4 x float>*
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%wide.load = load <4 x float>, <4 x float>* %1, align 4
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%2 = getelementptr float, float* %0, i64 4
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%3 = bitcast float* %2 to <4 x float>*
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%wide.load10 = load <4 x float>, <4 x float>* %3, align 4
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%4 = fadd fast <4 x float> %wide.load, %vec.phi
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%5 = fadd fast <4 x float> %wide.load10, %vec.phi9
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%index.next = add nuw nsw i64 %index, 8
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%6 = getelementptr inbounds float, float* %a, i64 %index.next
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%7 = bitcast float* %6 to <4 x float>*
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%wide.load.1 = load <4 x float>, <4 x float>* %7, align 4
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%8 = getelementptr float, float* %6, i64 4
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%9 = bitcast float* %8 to <4 x float>*
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%wide.load10.1 = load <4 x float>, <4 x float>* %9, align 4
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%10 = fadd fast <4 x float> %wide.load.1, %4
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%11 = fadd fast <4 x float> %wide.load10.1, %5
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%index.next.1 = add nsw i64 %index, 16
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%12 = getelementptr inbounds float, float* %a, i64 %index.next.1
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%13 = bitcast float* %12 to <4 x float>*
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%wide.load.2 = load <4 x float>, <4 x float>* %13, align 4
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%14 = getelementptr float, float* %12, i64 4
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%15 = bitcast float* %14 to <4 x float>*
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%wide.load10.2 = load <4 x float>, <4 x float>* %15, align 4
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%16 = fadd fast <4 x float> %wide.load.2, %10
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%17 = fadd fast <4 x float> %wide.load10.2, %11
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%index.next.2 = add nsw i64 %index, 24
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%18 = getelementptr inbounds float, float* %a, i64 %index.next.2
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%19 = bitcast float* %18 to <4 x float>*
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%wide.load.3 = load <4 x float>, <4 x float>* %19, align 4
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%20 = getelementptr float, float* %18, i64 4
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%21 = bitcast float* %20 to <4 x float>*
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%wide.load10.3 = load <4 x float>, <4 x float>* %21, align 4
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%22 = fadd fast <4 x float> %wide.load.3, %16
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%23 = fadd fast <4 x float> %wide.load10.3, %17
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%index.next.3 = add nsw i64 %index, 32
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%24 = getelementptr inbounds float, float* %a, i64 %index.next.3
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%25 = bitcast float* %24 to <4 x float>*
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%wide.load.4 = load <4 x float>, <4 x float>* %25, align 4
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%26 = getelementptr float, float* %24, i64 4
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%27 = bitcast float* %26 to <4 x float>*
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%wide.load10.4 = load <4 x float>, <4 x float>* %27, align 4
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%28 = fadd fast <4 x float> %wide.load.4, %22
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%29 = fadd fast <4 x float> %wide.load10.4, %23
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%index.next.4 = add nsw i64 %index, 40
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%30 = icmp eq i64 %index.next.4, 1000
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br i1 %30, label %middle.block, label %vector.body
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middle.block:
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%.lcssa15 = phi <4 x float> [ %29, %vector.body ]
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%.lcssa = phi <4 x float> [ %28, %vector.body ]
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%bin.rdx = fadd fast <4 x float> %.lcssa15, %.lcssa
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%rdx.shuf = shufflevector <4 x float> %bin.rdx, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%bin.rdx11 = fadd fast <4 x float> %bin.rdx, %rdx.shuf
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%rdx.shuf12 = shufflevector <4 x float> %bin.rdx11, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%bin.rdx13 = fadd fast <4 x float> %bin.rdx11, %rdx.shuf12
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%31 = extractelement <4 x float> %bin.rdx13, i32 0
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ret float %31
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}
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