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[SLP] avoid reduction transform on patterns that the backend can load-combine (2nd try)
The 1st attempt at this modified the cost model in a bad way to avoid the vectorization, but that caused problems for other users (the loop vectorizer) of the cost model. I don't see an ideal solution to these 2 related, potentially large, perf regressions: https://bugs.llvm.org/show_bug.cgi?id=42708 https://bugs.llvm.org/show_bug.cgi?id=43146 We decided that load combining was unsuitable for IR because it could obscure other optimizations in IR. So we removed the LoadCombiner pass and deferred to the backend. Therefore, preventing SLP from destroying load combine opportunities requires that it recognizes patterns that could be combined later, but not do the optimization itself ( it's not a vector combine anyway, so it's probably out-of-scope for SLP). Here, we add a cost-independent bailout with a conservative pattern match for a multi-instruction sequence that can probably be reduced later. In the x86 tests shown (and discussed in more detail in the bug reports), SDAG combining will produce a single instruction on these tests like: movbe rax, qword ptr [rdi] or: mov rax, qword ptr [rdi] Not some (half) vector monstrosity as we currently do using SLP: vpmovzxbq ymm0, dword ptr [rdi + 1] # ymm0 = mem[0],zero,zero,.. vpsllvq ymm0, ymm0, ymmword ptr [rip + .LCPI0_0] movzx eax, byte ptr [rdi] movzx ecx, byte ptr [rdi + 5] shl rcx, 40 movzx edx, byte ptr [rdi + 6] shl rdx, 48 or rdx, rcx movzx ecx, byte ptr [rdi + 7] shl rcx, 56 or rcx, rdx or rcx, rax vextracti128 xmm1, ymm0, 1 vpor xmm0, xmm0, xmm1 vpshufd xmm1, xmm0, 78 # xmm1 = xmm0[2,3,0,1] vpor xmm0, xmm0, xmm1 vmovq rax, xmm0 or rax, rcx vzeroupper ret Differential Revision: https://reviews.llvm.org/D67841 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375025 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel
@@ -15,31 +15,37 @@ define i64 @load_bswap(%v8i8* %p) {
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; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 5
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; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 6
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; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 7
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[G0]] to <4 x i8>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
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; CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[G0]]
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; CHECK-NEXT: [[T1:%.*]] = load i8, i8* [[G1]]
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; CHECK-NEXT: [[T2:%.*]] = load i8, i8* [[G2]]
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; CHECK-NEXT: [[T3:%.*]] = load i8, i8* [[G3]]
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; CHECK-NEXT: [[T4:%.*]] = load i8, i8* [[G4]]
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; CHECK-NEXT: [[T5:%.*]] = load i8, i8* [[G5]]
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; CHECK-NEXT: [[T6:%.*]] = load i8, i8* [[G6]]
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; CHECK-NEXT: [[T7:%.*]] = load i8, i8* [[G7]]
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; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i64>
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; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[T0]] to i64
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; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[T1]] to i64
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; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64
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; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[T3]] to i64
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; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i64
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; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64
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; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i64
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; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = shl nuw <4 x i64> [[TMP3]], <i64 56, i64 48, i64 40, i64 32>
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; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 56
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; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48
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; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40
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; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32
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; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24
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; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16
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; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = or <4 x i64> [[TMP4]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x i64> [[BIN_RDX]], <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = or <4 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[BIN_RDX2]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], [[SH4]]
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; CHECK-NEXT: [[TMP7:%.*]] = or i64 [[TMP6]], [[SH5]]
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; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP7]], [[SH6]]
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; CHECK-NEXT: [[OP_EXTRA:%.*]] = or i64 [[TMP8]], [[Z7]]
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; CHECK-NEXT: ret i64 [[OP_EXTRA]]
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; CHECK-NEXT: [[OR01:%.*]] = or i64 [[SH0]], [[SH1]]
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; CHECK-NEXT: [[OR012:%.*]] = or i64 [[OR01]], [[SH2]]
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; CHECK-NEXT: [[OR0123:%.*]] = or i64 [[OR012]], [[SH3]]
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; CHECK-NEXT: [[OR01234:%.*]] = or i64 [[OR0123]], [[SH4]]
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; CHECK-NEXT: [[OR012345:%.*]] = or i64 [[OR01234]], [[SH5]]
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; CHECK-NEXT: [[OR0123456:%.*]] = or i64 [[OR012345]], [[SH6]]
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; CHECK-NEXT: [[OR01234567:%.*]] = or i64 [[OR0123456]], [[Z7]]
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; CHECK-NEXT: ret i64 [[OR01234567]]
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;
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%g0 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 0
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%g1 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 1
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@@ -97,18 +103,38 @@ define i64 @load_bswap_nop_shift(%v8i8* %p) {
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; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 5
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; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 6
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; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 7
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[G0]] to <8 x i8>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
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; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i64>
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; CHECK-NEXT: [[TMP4:%.*]] = shl nuw <8 x i64> [[TMP3]], <i64 56, i64 48, i64 40, i64 32, i64 24, i64 16, i64 8, i64 0>
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = or <8 x i64> [[TMP4]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i64> [[BIN_RDX]], <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = or <8 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i64> [[BIN_RDX2]], <8 x i64> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX4:%.*]] = or <8 x i64> [[BIN_RDX2]], [[RDX_SHUF3]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i64> [[BIN_RDX4]], i32 0
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; CHECK-NEXT: ret i64 [[TMP5]]
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; CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[G0]]
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; CHECK-NEXT: [[T1:%.*]] = load i8, i8* [[G1]]
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; CHECK-NEXT: [[T2:%.*]] = load i8, i8* [[G2]]
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; CHECK-NEXT: [[T3:%.*]] = load i8, i8* [[G3]]
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; CHECK-NEXT: [[T4:%.*]] = load i8, i8* [[G4]]
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; CHECK-NEXT: [[T5:%.*]] = load i8, i8* [[G5]]
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; CHECK-NEXT: [[T6:%.*]] = load i8, i8* [[G6]]
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; CHECK-NEXT: [[T7:%.*]] = load i8, i8* [[G7]]
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; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[T0]] to i64
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; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[T1]] to i64
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; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64
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; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[T3]] to i64
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; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i64
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; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64
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; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i64
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; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i64
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; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 56
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; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48
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; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40
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; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32
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; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24
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; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16
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; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8
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; CHECK-NEXT: [[SH7:%.*]] = shl nuw nsw i64 [[Z7]], 0
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; CHECK-NEXT: [[OR01:%.*]] = or i64 [[SH0]], [[SH1]]
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; CHECK-NEXT: [[OR012:%.*]] = or i64 [[OR01]], [[SH2]]
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; CHECK-NEXT: [[OR0123:%.*]] = or i64 [[OR012]], [[SH3]]
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; CHECK-NEXT: [[OR01234:%.*]] = or i64 [[OR0123]], [[SH4]]
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; CHECK-NEXT: [[OR012345:%.*]] = or i64 [[OR01234]], [[SH5]]
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; CHECK-NEXT: [[OR0123456:%.*]] = or i64 [[OR012345]], [[SH6]]
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; CHECK-NEXT: [[OR01234567:%.*]] = or i64 [[OR0123456]], [[SH7]]
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; CHECK-NEXT: ret i64 [[OR01234567]]
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;
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%g0 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 0
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%g1 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 1
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@@ -168,30 +194,36 @@ define i64 @load64le(i8* %arg) {
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; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 6
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; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 7
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; CHECK-NEXT: [[LD0:%.*]] = load i8, i8* [[ARG]], align 1
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[G1]] to <4 x i8>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
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; CHECK-NEXT: [[LD1:%.*]] = load i8, i8* [[G1]], align 1
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; CHECK-NEXT: [[LD2:%.*]] = load i8, i8* [[G2]], align 1
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; CHECK-NEXT: [[LD3:%.*]] = load i8, i8* [[G3]], align 1
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; CHECK-NEXT: [[LD4:%.*]] = load i8, i8* [[G4]], align 1
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; CHECK-NEXT: [[LD5:%.*]] = load i8, i8* [[G5]], align 1
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; CHECK-NEXT: [[LD6:%.*]] = load i8, i8* [[G6]], align 1
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; CHECK-NEXT: [[LD7:%.*]] = load i8, i8* [[G7]], align 1
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; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i64>
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; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64
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; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64
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; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[LD3]] to i64
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; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[LD4]] to i64
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; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64
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; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64
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; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = shl nuw nsw <4 x i64> [[TMP3]], <i64 8, i64 16, i64 24, i64 32>
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; CHECK-NEXT: [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8
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; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16
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; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i64 [[Z3]], 24
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; CHECK-NEXT: [[S4:%.*]] = shl nuw nsw i64 [[Z4]], 32
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; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40
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; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48
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; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = or <4 x i64> [[TMP4]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x i64> [[BIN_RDX]], <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = or <4 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[BIN_RDX2]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], [[S5]]
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; CHECK-NEXT: [[TMP7:%.*]] = or i64 [[TMP6]], [[S6]]
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; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP7]], [[S7]]
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; CHECK-NEXT: [[OP_EXTRA:%.*]] = or i64 [[TMP8]], [[Z0]]
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; CHECK-NEXT: ret i64 [[OP_EXTRA]]
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; CHECK-NEXT: [[O1:%.*]] = or i64 [[S1]], [[Z0]]
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; CHECK-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S2]]
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; CHECK-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S3]]
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; CHECK-NEXT: [[O4:%.*]] = or i64 [[O3]], [[S4]]
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; CHECK-NEXT: [[O5:%.*]] = or i64 [[O4]], [[S5]]
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; CHECK-NEXT: [[O6:%.*]] = or i64 [[O5]], [[S6]]
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; CHECK-NEXT: [[O7:%.*]] = or i64 [[O6]], [[S7]]
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; CHECK-NEXT: ret i64 [[O7]]
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;
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%g1 = getelementptr inbounds i8, i8* %arg, i64 1
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%g2 = getelementptr inbounds i8, i8* %arg, i64 2
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@@ -247,18 +279,38 @@ define i64 @load64le_nop_shift(i8* %arg) {
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; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 5
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; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 6
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; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 7
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[ARG]] to <8 x i8>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
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; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i64>
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; CHECK-NEXT: [[TMP4:%.*]] = shl nuw <8 x i64> [[TMP3]], <i64 0, i64 8, i64 16, i64 24, i64 32, i64 40, i64 48, i64 56>
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = or <8 x i64> [[TMP4]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i64> [[BIN_RDX]], <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = or <8 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i64> [[BIN_RDX2]], <8 x i64> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX4:%.*]] = or <8 x i64> [[BIN_RDX2]], [[RDX_SHUF3]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i64> [[BIN_RDX4]], i32 0
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; CHECK-NEXT: ret i64 [[TMP5]]
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; CHECK-NEXT: [[LD0:%.*]] = load i8, i8* [[ARG]], align 1
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; CHECK-NEXT: [[LD1:%.*]] = load i8, i8* [[G1]], align 1
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; CHECK-NEXT: [[LD2:%.*]] = load i8, i8* [[G2]], align 1
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; CHECK-NEXT: [[LD3:%.*]] = load i8, i8* [[G3]], align 1
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; CHECK-NEXT: [[LD4:%.*]] = load i8, i8* [[G4]], align 1
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; CHECK-NEXT: [[LD5:%.*]] = load i8, i8* [[G5]], align 1
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; CHECK-NEXT: [[LD6:%.*]] = load i8, i8* [[G6]], align 1
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; CHECK-NEXT: [[LD7:%.*]] = load i8, i8* [[G7]], align 1
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; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64
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; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64
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; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64
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; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[LD3]] to i64
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; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[LD4]] to i64
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; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64
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; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64
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; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64
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; CHECK-NEXT: [[S0:%.*]] = shl nuw nsw i64 [[Z0]], 0
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; CHECK-NEXT: [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8
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; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16
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; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i64 [[Z3]], 24
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; CHECK-NEXT: [[S4:%.*]] = shl nuw nsw i64 [[Z4]], 32
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; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40
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; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48
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; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56
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; CHECK-NEXT: [[O1:%.*]] = or i64 [[S1]], [[S0]]
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; CHECK-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S2]]
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; CHECK-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S3]]
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; CHECK-NEXT: [[O4:%.*]] = or i64 [[O3]], [[S4]]
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; CHECK-NEXT: [[O5:%.*]] = or i64 [[O4]], [[S5]]
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; CHECK-NEXT: [[O6:%.*]] = or i64 [[O5]], [[S6]]
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; CHECK-NEXT: [[O7:%.*]] = or i64 [[O6]], [[S7]]
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; CHECK-NEXT: ret i64 [[O7]]
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;
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%g1 = getelementptr inbounds i8, i8* %arg, i64 1
|
||||
%g2 = getelementptr inbounds i8, i8* %arg, i64 2
|
||||
|
||||
Reference in New Issue
Block a user