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Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Barton
parent
8f3d54d057
commit
b5523ce1bb
@ -1758,6 +1758,16 @@ def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
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let Inst{7-4} = 0b0111;
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}
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def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
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"hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
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bits<16> val;
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let Inst{3-0} = val{3-0};
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let Inst{19-8} = val{15-4};
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let Inst{27-20} = 0b00010000;
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let Inst{31-28} = 0xe; // AL
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let Inst{7-4} = 0b0111;
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}
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// Change Processor State
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// FIXME: We should use InstAlias to handle the optional operands.
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class CPS<dag iops, string asm_ops>
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@ -300,6 +300,13 @@ def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
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let Inst{7-0} = val;
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}
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def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
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[]>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
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let Inst{9-6} = 0b1010;
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bits<6> val;
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let Inst{5-0} = val;
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}
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def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
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[]>, T1Encoding<0b101101> {
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bits<1> end;
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@ -3645,6 +3645,20 @@ def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
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let Inst{19-16} = opt;
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}
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class T2DCPS<bits<2> opt, string opc>
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: T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
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let Inst{31-27} = 0b11110;
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let Inst{26-20} = 0b1111000;
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let Inst{19-16} = 0b1111;
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let Inst{15-12} = 0b1000;
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let Inst{11-2} = 0b0000000000;
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let Inst{1-0} = opt;
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}
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def t2DCPS1 : T2DCPS<0b01, "dcps1">;
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def t2DCPS2 : T2DCPS<0b10, "dcps2">;
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def t2DCPS3 : T2DCPS<0b11, "dcps3">;
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class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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@ -4687,7 +4687,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
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Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
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Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
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Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
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Mnemonic == "vaclt" || Mnemonic == "vacle" ||
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Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
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Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
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Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
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Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
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@ -4793,7 +4793,7 @@ getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
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Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
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Mnemonic == "trap" || Mnemonic == "setend" ||
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Mnemonic == "trap" || Mnemonic == "hlt" ||
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Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
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Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
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Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
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@ -5297,6 +5297,16 @@ static const MCInstrDesc &getInstDesc(unsigned Opcode) {
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return ARMInsts[Opcode];
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}
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// Return true if instruction has the interesting property of being
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// allowed in IT blocks, but not being predicable.
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static bool instIsBreakpoint(const MCInst &Inst) {
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return Inst.getOpcode() == ARM::tBKPT ||
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Inst.getOpcode() == ARM::BKPT ||
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Inst.getOpcode() == ARM::tHLT ||
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Inst.getOpcode() == ARM::HLT;
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}
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// FIXME: We would really like to be able to tablegen'erate this.
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bool ARMAsmParser::
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validateInstruction(MCInst &Inst,
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@ -5305,11 +5315,10 @@ validateInstruction(MCInst &Inst,
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SMLoc Loc = Operands[0]->getStartLoc();
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// Check the IT block state first.
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// NOTE: BKPT instruction has the interesting property of being
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// allowed in IT blocks, but not being predicable. It just always
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// executes.
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if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
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Inst.getOpcode() != ARM::BKPT) {
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// NOTE: BKPT and HLT instructions have the interesting property of being
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// allowed in IT blocks, but not being predicable. They just always
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// execute.
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if (inITBlock() && !instIsBreakpoint(Inst)) {
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unsigned bit = 1;
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if (ITState.FirstCond)
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ITState.FirstCond = false;
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17
test/MC/ARM/basic-arm-instructions-v8.s
Normal file
17
test/MC/ARM/basic-arm-instructions-v8.s
Normal file
@ -0,0 +1,17 @@
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@ New ARMv8 A32 encodings
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@ RUN: llvm-mc -triple armv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
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@ RUN: not llvm-mc -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
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@ HLT
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hlt #0
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hlt #65535
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@ CHECK-V8: hlt #0 @ encoding: [0x70,0x00,0x00,0xe1]
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@ CHECK-V8: hlt #65535 @ encoding: [0x7f,0xff,0x0f,0xe1]
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ AL condition code allowable
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hltal #0
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@ CHECK-V8: hlt #0 @ encoding: [0x70,0x00,0x00,0xe1]
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@ CHECK-V7: error: instruction requires: armv8
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36
test/MC/ARM/basic-thumb2-instructions-v8.s
Normal file
36
test/MC/ARM/basic-thumb2-instructions-v8.s
Normal file
@ -0,0 +1,36 @@
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@ New ARMv8 T32 encodings
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@ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
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@ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
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@ HLT
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hlt #0
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hlt #63
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@ CHECK-V8: hlt #0 @ encoding: [0x80,0xba]
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@ CHECK-V8: hlt #63 @ encoding: [0xbf,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ In IT block
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it pl
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hlt #24
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@ CHECK-V8: it pl @ encoding: [0x58,0xbf]
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@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ Can accept AL condition code
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hltal #24
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@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ DCPS{1,2,3}
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dcps1
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dcps2
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dcps3
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@ CHECK-V8: dcps1 @ encoding: [0x8f,0xf7,0x01,0x80]
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@ CHECK-V8: dcps2 @ encoding: [0x8f,0xf7,0x02,0x80]
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@ CHECK-V8: dcps3 @ encoding: [0x8f,0xf7,0x03,0x80]
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ -1,5 +1,7 @@
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@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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@ RUN: not llvm-mc -triple=armv8 < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ Check for various assembly diagnostic messages on invalid input.
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@ -93,6 +95,26 @@
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediates for v8 HLT instruction.
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hlt #65536
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hlt #-1
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@CHECK-ERRORS-V8: error: invalid operand for instruction
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@CHECK-ERRORS-V8: hlt #65536
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS-V8: error: invalid operand for instruction
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@CHECK-ERRORS-V8: hlt #-1
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@CHECK-ERRORS-V8: ^
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@ Illegal condition code for v8 HLT instruction.
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hlteq #2
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hltlt #23
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@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS-V8: hlteq #2
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS-V8: hltlt #23
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@CHECK-ERRORS-V8: ^
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@ Out of range 4 and 3 bit immediates on CDP[2]
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@ Out of range immediates for CDP/CDP2
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@ -2,6 +2,8 @@
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
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@ RUN: not llvm-mc -triple=thumbv8 < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ Check for various assembly diagnostic messages on invalid input.
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@ -38,6 +40,19 @@ error: invalid operand for instruction
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bkpt #-1
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^
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@ Out of range immediates for v8 HLT instruction.
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hlt #64
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hlt #-1
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@CHECK-ERRORS: error: instruction requires: armv8 arm-mode
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@CHECK-ERRORS: hlt #64
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@CHECK-ERRORS: ^
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@CHECK-ERRORS-V8: error: instruction requires: arm-mode
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@CHECK-ERRORS-V8: hlt #64
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS: error: invalid operand for instruction
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@CHECK-ERRORS: hlt #-1
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@CHECK-ERRORS: ^
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@ Invalid writeback and register lists for LDM
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ldm r2!, {r5, r8}
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ldm r2, {r5, r7}
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11
test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
Normal file
11
test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
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@ -0,0 +1,11 @@
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# RUN: llvm-mc -disassemble -triple armv8 -show-encoding < %s | FileCheck %s
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# New v8 ARM instructions
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# HLT
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0x70 0x00 0x00 0xe1
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# CHECK: hlt #0
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0x7f 0xff 0x0f 0xe1
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# CHECK: hlt #65535
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18
test/MC/Disassembler/ARM/thumb-v8.txt
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18
test/MC/Disassembler/ARM/thumb-v8.txt
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@ -0,0 +1,18 @@
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# RUN: llvm-mc -disassemble -triple thumbv8 -show-encoding < %s | FileCheck %s
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0x80 0xba
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# CHECK: hlt #0
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0xbf 0xba
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# CHECK: hlt #63
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# DCPS{1,2,3}
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0x8f 0xf7 0x01 0x80
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# CHECK: dcps1
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0x8f 0xf7 0x02 0x80
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# CHECK: dcps2
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0x8f 0xf7 0x03 0x80
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# CHECK: dcps3
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