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R600/SI: Set hasSideEffects = 0 on load and store instructions.

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Assuming unmodeled side effects interferes with some scheduling
opportunities.

Don't put it in the base class of DS instructions since there
are a few weird effecting, non load/store instructions there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222285 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-11-18 23:57:33 +00:00
parent e6d1a2625f
commit b556213712
2 changed files with 9 additions and 4 deletions
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8
lib/Target/R600/SIInstrFormats.td
View File

@ -223,6 +223,7 @@ class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
let SMRD = 1; let SMRD = 1;
let mayStore = 0; let mayStore = 0;
let mayLoad = 1; let mayLoad = 1;
let hasSideEffects = 0;
let UseNamedOperandTable = 1; let UseNamedOperandTable = 1;
} }
@ -527,10 +528,9 @@ class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> : class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern>, VINTRPe<op> { InstSI <outs, ins, asm, pattern>, VINTRPe<op> {
let neverHasSideEffects = 1;
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0;
} }
} // End Uses = [EXEC] } // End Uses = [EXEC]
@ -555,7 +555,7 @@ class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
let EXP_CNT = 1; let EXP_CNT = 1;
let MUBUF = 1; let MUBUF = 1;
let neverHasSideEffects = 1; let hasSideEffects = 0;
let UseNamedOperandTable = 1; let UseNamedOperandTable = 1;
} }
@ -591,6 +591,8 @@ class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
let VM_CNT = 1; let VM_CNT = 1;
let EXP_CNT = 1; let EXP_CNT = 1;
let MIMG = 1; let MIMG = 1;
let hasSideEffects = 0; // XXX ????
} }

5
lib/Target/R600/SIInstrInfo.td
View File

@ -941,6 +941,8 @@ class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
// Single load interpret the 2 i8imm operands as a single i16 offset. // Single load interpret the 2 i8imm operands as a single i16 offset.
let offset0 = offset{7-0}; let offset0 = offset{7-0};
let offset1 = offset{15-8}; let offset1 = offset{15-8};
let hasSideEffects = 0;
} }
class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
@ -965,6 +967,7 @@ class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
let data1 = 0; let data1 = 0;
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0;
} }
class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
@ -988,6 +991,7 @@ class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
[]> { []> {
let mayStore = 1; let mayStore = 1;
let mayLoad = 0; let mayLoad = 0;
let hasSideEffects = 0;
let vdst = 0; let vdst = 0;
} }
@ -1016,7 +1020,6 @@ class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""
AtomicNoRet<noRetOp, 1> { AtomicNoRet<noRetOp, 1> {
let mayStore = 1; let mayStore = 1;
let mayLoad = 1; let mayLoad = 1;
let hasPostISelHook = 1; // Adjusted to no return version. let hasPostISelHook = 1; // Adjusted to no return version.
} }