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Add stack spill / reload instructions for DTriple and DQuad register classes, which
were missed for no reason. This fixes PR13377 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
087642f863
commit
b58d7d0312
@ -795,8 +795,28 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 24:
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if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
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// Use aligned spills if the stack can be realigned.
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
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.addFrameIndex(FI).addImm(16)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO));
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} else {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
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.addFrameIndex(FI))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
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}
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 32:
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if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
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if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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// FIXME: It's possible to only store part of the QQ register if the
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// spilled def has a sub-register index.
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@ -942,8 +962,28 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 32:
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if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
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case 24:
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if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
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.addFrameIndex(FI).addImm(16)
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.addMemOperand(MMO));
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} else {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
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.addFrameIndex(FI)
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.addMemOperand(MMO));
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MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
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if (TargetRegisterInfo::isPhysicalRegister(DestReg))
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MIB.addReg(DestReg, RegState::ImplicitDefine);
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}
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 32:
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if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
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.addFrameIndex(FI).addImm(16)
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174
test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
Normal file
174
test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
Normal file
@ -0,0 +1,174 @@
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; RUN: llc < %s
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; PR13377
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7-none-linux-gnueabi"
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%0 = type { <4 x float> }
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define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable {
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br i1 undef, label %4, label %5
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; <label>:4 ; preds = %3
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unreachable
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; <label>:5 ; preds = %3
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br i1 undef, label %7, label %6
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; <label>:6 ; preds = %5
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unreachable
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; <label>:7 ; preds = %5
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br i1 undef, label %8, label %10
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; <label>:8 ; preds = %7
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br i1 undef, label %9, label %10
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; <label>:9 ; preds = %8
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br i1 undef, label %11, label %10
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; <label>:10 ; preds = %9, %8, %7
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unreachable
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; <label>:11 ; preds = %9
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br i1 undef, label %13, label %12
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; <label>:12 ; preds = %11
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unreachable
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; <label>:13 ; preds = %11
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br i1 undef, label %15, label %14
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; <label>:14 ; preds = %13
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unreachable
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; <label>:15 ; preds = %13
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br i1 undef, label %18, label %16
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; <label>:16 ; preds = %15
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br i1 undef, label %17, label %18
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; <label>:17 ; preds = %16
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unreachable
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; <label>:18 ; preds = %16, %15
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br i1 undef, label %68, label %19
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; <label>:19 ; preds = %18
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br label %20
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; <label>:20 ; preds = %20, %19
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br i1 undef, label %21, label %20
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; <label>:21 ; preds = %20
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br i1 undef, label %22, label %68
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; <label>:22 ; preds = %21
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br i1 undef, label %23, label %24
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; <label>:23 ; preds = %22
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unreachable
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; <label>:24 ; preds = %22
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br i1 undef, label %26, label %25
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; <label>:25 ; preds = %24
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unreachable
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; <label>:26 ; preds = %24
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br i1 undef, label %28, label %27
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; <label>:27 ; preds = %26
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unreachable
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; <label>:28 ; preds = %26
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br i1 undef, label %29, label %30, !prof !0
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; <label>:29 ; preds = %28
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br label %30
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; <label>:30 ; preds = %29, %28
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br i1 undef, label %31, label %32, !prof !0
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; <label>:31 ; preds = %30
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br label %32
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; <label>:32 ; preds = %31, %30
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br i1 undef, label %34, label %33
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; <label>:33 ; preds = %32
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unreachable
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; <label>:34 ; preds = %32
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br i1 undef, label %35, label %36, !prof !0
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; <label>:35 ; preds = %34
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br label %36
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; <label>:36 ; preds = %35, %34
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br i1 undef, label %37, label %38, !prof !0
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; <label>:37 ; preds = %36
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br label %38
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; <label>:38 ; preds = %37, %36
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br i1 undef, label %39, label %67
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; <label>:39 ; preds = %38
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br i1 undef, label %40, label %41
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; <label>:40 ; preds = %39
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br i1 undef, label %64, label %41
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; <label>:41 ; preds = %40, %39
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br i1 undef, label %64, label %42
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; <label>:42 ; preds = %41
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%43 = fadd <4 x float> undef, undef
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%44 = fadd <4 x float> undef, undef
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%45 = fmul <4 x float> undef, undef
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%46 = fmul <4 x float> %45, %43
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%47 = fmul <4 x float> undef, %44
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%48 = load <4 x float>* undef, align 8, !tbaa !1
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%49 = bitcast <4 x float> %48 to <2 x i64>
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%50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1>
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%51 = bitcast <1 x i64> %50 to <2 x float>
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%52 = shufflevector <2 x float> %51, <2 x float> undef, <4 x i32> zeroinitializer
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%53 = bitcast <4 x float> %52 to <2 x i64>
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%54 = shufflevector <2 x i64> %53, <2 x i64> undef, <1 x i32> zeroinitializer
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%55 = bitcast <1 x i64> %54 to <2 x float>
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%56 = extractelement <2 x float> %55, i32 0
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%57 = insertelement <4 x float> undef, float %56, i32 2
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%58 = insertelement <4 x float> %57, float 1.000000e+00, i32 3
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%59 = fsub <4 x float> %47, %58
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%60 = fmul <4 x float> undef, undef
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%61 = fmul <4 x float> %59, %60
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%62 = fmul <4 x float> %61, <float 6.000000e+01, float 6.000000e+01, float 6.000000e+01, float 6.000000e+01>
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%63 = fadd <4 x float> %47, %62
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store <4 x float> %46, <4 x float>* undef, align 8, !tbaa !1
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call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
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call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
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store <4 x float> %63, <4 x float>* undef, align 8, !tbaa !1
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unreachable
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; <label>:64 ; preds = %41, %40
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br i1 undef, label %65, label %66
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; <label>:65 ; preds = %64
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unreachable
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; <label>:66 ; preds = %64
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unreachable
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; <label>:67 ; preds = %38
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unreachable
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; <label>:68 ; preds = %21, %18
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ret void
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}
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declare arm_aapcs_vfpcc void @bar(%0*, float)
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!0 = metadata !{metadata !"branch_weights", i32 64, i32 4}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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