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Adjust PPC440 operand latencies
The operand latencies for the PPC440 should be specified relative to dispatch, not relative to the initial fetch-and-decode stages. Because most instructions (ignoring bypass) wait in dispatch until their operands are ready, this is modeled as reading input operands "at dispatch" (0 cycles after issue), and so every input and output operand has 4 cycles subtracted from it. This could alter scheduling slightly, but I don't expect a large effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195947 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
f13a4e6e7b
commit
b5ff1bb218
@ -110,7 +110,7 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[6, 4, 4],
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[2, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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@ -118,7 +118,7 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[6, 4, 4],
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[2, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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@ -126,21 +126,21 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[6, 4, 4],
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[2, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<33, [P440_IWB]>],
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[40, 4, 4],
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[36, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[7, 4, 4],
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[3, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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@ -148,7 +148,7 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[7, 4, 4],
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[3, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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@ -156,28 +156,28 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[8, 4, 4],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[8, 4, 4],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[8, 4, 4],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC, P440_LRACC]>,
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[6, 4, 4],
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[2, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntShift, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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@ -185,7 +185,7 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[6, 4, 4],
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[2, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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@ -193,140 +193,140 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[6, 4],
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[2, 0],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_BrB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[8, 4],
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[4, 0],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_BrCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[8, 4, 4],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[8, 4, 4],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[8, 4, 4],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[9, 5],
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[5, 1],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[9, 5],
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[5, 1],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5, 5],
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[4, 1, 1],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5, 5],
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[4, 1, 1],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[9, 5, 5],
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[5, 1, 1],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[9, 5, 5],
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[5, 1, 1],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_DISS1]>,
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InstrStage<1, [P440_IRACC], 0>,
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@ -335,21 +335,21 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
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InstrStage<1, [P440_IRACC], 0>,
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@ -358,7 +358,7 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_DISS1]>,
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InstrStage<1, [P440_IRACC], 0>,
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@ -367,7 +367,7 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[8, 5],
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[4, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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@ -395,21 +395,21 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[6, 4],
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[2, 0],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[6, 4],
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[2, 0],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<3, [P440_IWB]>],
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[9, 4],
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[5, 0],
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[NoBypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_IRACC]>,
|
||||
@ -421,56 +421,56 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [P440_IEXE1]>,
|
||||
InstrStage<1, [P440_IEXE2]>,
|
||||
InstrStage<1, [P440_IWB]>],
|
||||
[8, 4],
|
||||
[4, 0],
|
||||
[NoBypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_IRACC]>,
|
||||
InstrStage<1, [P440_IEXE1]>,
|
||||
InstrStage<1, [P440_IEXE2]>,
|
||||
InstrStage<1, [P440_IWB]>],
|
||||
[7, 4],
|
||||
[3, 0],
|
||||
[P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_IRACC]>,
|
||||
InstrStage<1, [P440_IEXE1]>,
|
||||
InstrStage<1, [P440_IEXE2]>,
|
||||
InstrStage<3, [P440_IWB]>],
|
||||
[10, 4],
|
||||
[6, 0],
|
||||
[NoBypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_IRACC]>,
|
||||
InstrStage<1, [P440_IEXE1]>,
|
||||
InstrStage<1, [P440_IEXE2]>,
|
||||
InstrStage<3, [P440_IWB]>],
|
||||
[10, 4],
|
||||
[6, 0],
|
||||
[NoBypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_IRACC]>,
|
||||
InstrStage<1, [P440_IEXE1]>,
|
||||
InstrStage<1, [P440_IEXE2]>,
|
||||
InstrStage<3, [P440_IWB]>],
|
||||
[10, 4],
|
||||
[6, 0],
|
||||
[NoBypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_IRACC]>,
|
||||
InstrStage<1, [P440_IEXE1]>,
|
||||
InstrStage<1, [P440_IEXE2]>,
|
||||
InstrStage<3, [P440_IWB]>],
|
||||
[10, 4],
|
||||
[6, 0],
|
||||
[NoBypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_IRACC]>,
|
||||
InstrStage<1, [P440_IEXE1]>,
|
||||
InstrStage<1, [P440_IEXE2]>,
|
||||
InstrStage<1, [P440_IWB]>],
|
||||
[8, 4],
|
||||
[4, 0],
|
||||
[NoBypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprSC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_IRACC]>,
|
||||
InstrStage<1, [P440_IEXE1]>,
|
||||
InstrStage<1, [P440_IEXE2]>,
|
||||
InstrStage<1, [P440_IWB]>],
|
||||
[8, 4],
|
||||
[4, 0],
|
||||
[NoBypass, P440_GPR_Bypass]>,
|
||||
InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_FRACC]>,
|
||||
@ -481,7 +481,7 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [P440_FEXE5]>,
|
||||
InstrStage<1, [P440_FEXE6]>,
|
||||
InstrStage<1, [P440_FWB]>],
|
||||
[10, 4, 4],
|
||||
[6, 0, 0],
|
||||
[P440_FPR_Bypass,
|
||||
P440_FPR_Bypass, P440_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
@ -493,7 +493,7 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [P440_FEXE5]>,
|
||||
InstrStage<1, [P440_FEXE6]>,
|
||||
InstrStage<1, [P440_FWB]>],
|
||||
[10, 4, 4],
|
||||
[6, 0, 0],
|
||||
[P440_FPR_Bypass,
|
||||
P440_FPR_Bypass, P440_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
@ -505,7 +505,7 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [P440_FEXE5]>,
|
||||
InstrStage<1, [P440_FEXE6]>,
|
||||
InstrStage<1, [P440_FWB]>],
|
||||
[10, 4, 4],
|
||||
[6, 0, 0],
|
||||
[P440_FPR_Bypass, P440_FPR_Bypass,
|
||||
P440_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
@ -517,7 +517,7 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [P440_FEXE5]>,
|
||||
InstrStage<1, [P440_FEXE6]>,
|
||||
InstrStage<25, [P440_FWB]>],
|
||||
[35, 4, 4],
|
||||
[31, 0, 0],
|
||||
[NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_FRACC]>,
|
||||
@ -528,7 +528,7 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [P440_FEXE5]>,
|
||||
InstrStage<1, [P440_FEXE6]>,
|
||||
InstrStage<13, [P440_FWB]>],
|
||||
[23, 4, 4],
|
||||
[19, 0, 0],
|
||||
[NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPFused, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||||
InstrStage<1, [P440_FRACC]>,
|
||||
@ -539,7 +539,7 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [P440_FEXE5]>,
|
||||
InstrStage<1, [P440_FEXE6]>,
|
||||
InstrStage<1, [P440_FWB]>],
|
||||
[10, 4, 4, 4],
|
||||
[6, 0, 0, 0],
|
||||
[P440_FPR_Bypass,
|
||||
P440_FPR_Bypass, P440_FPR_Bypass,
|
||||
P440_FPR_Bypass]>,
|
||||
@ -552,6 +552,6 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [P440_FEXE5]>,
|
||||
InstrStage<1, [P440_FEXE6]>,
|
||||
InstrStage<1, [P440_FWB]>],
|
||||
[10, 4],
|
||||
[6, 0],
|
||||
[P440_FPR_Bypass, P440_FPR_Bypass]>
|
||||
]>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user