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relax an assertion a bit, allowing the GPR argument of

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these instructions to be encoded with getMachineOpValue.
This unbreaks ExecutionEngine/2003-01-04-ArgumentBug.ll 
when running on a G5


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119307 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-11-16 00:55:51 +00:00
parent b55e91e087
commit b69cdfa6f3
2 changed files with 6 additions and 2 deletions
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5
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -246,7 +246,10 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) const {
if (MO.isReg()) {
assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
// MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
// The GPR operand should come through here though.
assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
}

3
lib/Target/PowerPC/PPCMCCodeEmitter.cpp
View File

@ -199,7 +199,8 @@ unsigned PPCMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const {
if (MO.isReg()) {
assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
}