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Add LLVM support for PPC cryptography builtins
Review: http://reviews.llvm.org/D7955 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231285 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic
parent
c56226c6d1
commit
b69d556c37
@ -73,7 +73,7 @@ class PowerPC_Vec_FFF_Intrinsic<string GCCIntSuffix>
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[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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/// PowerPC_Vec_BBB_Intrinsic - A PowerPC intrinsic that takes two v16f8
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/// PowerPC_Vec_BBB_Intrinsic - A PowerPC intrinsic that takes two v16i8
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/// vectors and returns one. These intrinsics have no side effects.
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class PowerPC_Vec_BBB_Intrinsic<string GCCIntSuffix>
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: PowerPC_Vec_Intrinsic<GCCIntSuffix,
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@ -126,7 +126,6 @@ class PowerPC_VSX_Sca_DDD_Intrinsic<string GCCIntSuffix>
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[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
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[IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// PowerPC Altivec Intrinsic Definitions.
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@ -559,6 +558,41 @@ def int_ppc_altivec_vlogefp : PowerPC_Vec_FF_Intrinsic<"vlogefp">;
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def int_ppc_altivec_vrefp : PowerPC_Vec_FF_Intrinsic<"vrefp">;
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def int_ppc_altivec_vrsqrtefp : PowerPC_Vec_FF_Intrinsic<"vrsqrtefp">;
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// Power8 Intrinsics
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// Crypto
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let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
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def int_ppc_altivec_crypto_vsbox :
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GCCBuiltin<"__builtin_altivec_crypto_vsbox">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
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def int_ppc_altivec_crypto_vpermxor :
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GCCBuiltin<"__builtin_altivec_crypto_vpermxor">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
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llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
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// These need diagnostics for invalid arguments so don't inherit from GCCBuiltin
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def int_ppc_altivec_crypto_vshasigmad :
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
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llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_ppc_altivec_crypto_vshasigmaw :
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
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llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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}
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def int_ppc_altivec_crypto_vcipher :
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PowerPC_Vec_DDD_Intrinsic<"crypto_vcipher">;
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def int_ppc_altivec_crypto_vcipherlast :
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PowerPC_Vec_DDD_Intrinsic<"crypto_vcipherlast">;
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def int_ppc_altivec_crypto_vncipher :
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PowerPC_Vec_DDD_Intrinsic<"crypto_vncipher">;
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def int_ppc_altivec_crypto_vncipherlast :
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PowerPC_Vec_DDD_Intrinsic<"crypto_vncipherlast">;
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def int_ppc_altivec_crypto_vpmsumb :
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PowerPC_Vec_BBB_Intrinsic<"crypto_vpmsumb">;
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def int_ppc_altivec_crypto_vpmsumh :
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PowerPC_Vec_HHH_Intrinsic<"crypto_vpmsumh">;
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def int_ppc_altivec_crypto_vpmsumw :
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PowerPC_Vec_WWW_Intrinsic<"crypto_vpmsumw">;
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def int_ppc_altivec_crypto_vpmsumd :
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PowerPC_Vec_DDD_Intrinsic<"crypto_vpmsumd">;
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//===----------------------------------------------------------------------===//
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// PowerPC VSX Intrinsic Definitions.
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@ -425,6 +425,7 @@ public:
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bool isToken() const override { return Kind == Token; }
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bool isImm() const override { return Kind == Immediate || Kind == Expression; }
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bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
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bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
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bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
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bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
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@ -214,6 +214,13 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
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printOperand(MI, OpNo+1, O);
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}
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void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 1 && "Invalid u1imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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@ -43,6 +43,7 @@ public:
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void printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier = nullptr);
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void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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@ -112,6 +112,9 @@ def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
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def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
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"Enable POWER8 Altivec instructions",
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[FeatureAltivec]>;
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def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
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"Enable POWER8 Crypto instructions",
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[FeatureP8Altivec]>;
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def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
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"Enable POWER8 vector instructions",
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[FeatureVSX, FeatureP8Altivec]>;
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@ -258,7 +261,7 @@ def ProcessorFeatures {
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FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
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FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
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FeatureFPRND, FeatureFPCVT, FeatureISEL,
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FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
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FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, FeatureP8Crypto,
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Feature64Bit /*, Feature64BitRegs */, FeatureICBT,
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DeprecatedMFTB, DeprecatedDST];
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}
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@ -269,6 +269,16 @@ class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
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!strconcat(opc, " $vD, $vB"), IIC_VecFP,
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[(set OutTy:$vD, (IntID InTy:$vB))]>;
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class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
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: VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA),
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!strconcat(opc, " $vD, $vA"), IIC_VecFP,
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[(set Ty:$vD, (IntID Ty:$vA))]>;
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class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
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: VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX),
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!strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP,
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[(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>;
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//===----------------------------------------------------------------------===//
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// Instruction Definitions.
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@ -939,6 +949,7 @@ def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
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} // end HasAltivec
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def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
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def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
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let Predicates = [HasP8Altivec] in {
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let isCommutable = 1 in {
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@ -1035,4 +1046,33 @@ def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
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def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>;
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def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
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// The cryptography instructions that do not require Category:Vector.Crypto
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def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
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int_ppc_altivec_crypto_vpmsumb, v16i8>;
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def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
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int_ppc_altivec_crypto_vpmsumh, v8i16>;
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def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
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int_ppc_altivec_crypto_vpmsumw, v4i32>;
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def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
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int_ppc_altivec_crypto_vpmsumd, v2i64>;
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def VPERMXOR : VA1a_Int_Ty<45, "vpermxor",
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int_ppc_altivec_crypto_vpermxor, v16i8>;
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} // end HasP8Altivec
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// Crypto instructions (from builtins)
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let Predicates = [HasP8Crypto] in {
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def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw",
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int_ppc_altivec_crypto_vshasigmaw, v4i32>;
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def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad",
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int_ppc_altivec_crypto_vshasigmad, v2i64>;
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def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher,
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v2i64>;
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def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
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int_ppc_altivec_crypto_vcipherlast, v2i64>;
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def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
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int_ppc_altivec_crypto_vncipher, v2i64>;
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def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
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int_ppc_altivec_crypto_vncipherlast, v2i64>;
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def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
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} // HasP8Crypto
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@ -1470,6 +1470,39 @@ class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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let Inst{21-31} = xo;
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}
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/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
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class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OOL, IOL, asmstr, itin> {
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bits<5> VD;
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bits<5> VA;
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bits<1> ST;
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bits<4> SIX;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16} = ST;
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let Inst{17-20} = SIX;
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let Inst{21-31} = xo;
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}
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/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
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class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OOL, IOL, asmstr, itin> {
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bits<5> VD;
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bits<5> VA;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16-20} = 0;
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let Inst{21-31} = xo;
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}
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// E-4 VXR-Form
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class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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@ -446,6 +446,15 @@ def crrc : RegisterOperand<CRRC> {
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let ParserMatchClass = PPCRegCRRCAsmOperand;
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}
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def PPCU1ImmAsmOperand : AsmOperandClass {
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let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
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let RenderMethod = "addImmOperands";
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}
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def u1imm : Operand<i32> {
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let PrintMethod = "printU1ImmOperand";
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let ParserMatchClass = PPCU1ImmAsmOperand;
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}
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def PPCU2ImmAsmOperand : AsmOperandClass {
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let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
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let RenderMethod = "addImmOperands";
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@ -69,6 +69,7 @@ void PPCSubtarget::initializeEnvironment() {
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HasVSX = false;
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HasP8Vector = false;
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HasP8Altivec = false;
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HasP8Crypto = false;
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HasFCPSGN = false;
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HasFSQRT = false;
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HasFRE = false;
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@ -90,6 +90,7 @@ protected:
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bool HasVSX;
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bool HasP8Vector;
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bool HasP8Altivec;
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bool HasP8Crypto;
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bool HasFCPSGN;
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bool HasFSQRT;
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bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
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@ -218,6 +219,7 @@ public:
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bool hasVSX() const { return HasVSX; }
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bool hasP8Vector() const { return HasP8Vector; }
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bool hasP8Altivec() const { return HasP8Altivec; }
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bool hasP8Crypto() const { return HasP8Crypto; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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bool hasISEL() const { return HasISEL; }
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bool hasPOPCNTD() const { return HasPOPCNTD; }
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@ -211,6 +211,51 @@ vector float f(vector float a, vector float b) {
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//===----------------------------------------------------------------------===//
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We should do a little better with eliminating dead stores.
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The stores to the stack are dead since %a and %b are not needed
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; Function Attrs: nounwind
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define <16 x i8> @test_vpmsumb() #0 {
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entry:
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%a = alloca <16 x i8>, align 16
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%b = alloca <16 x i8>, align 16
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store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %a, align 16
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store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %b, align 16
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%0 = load <16 x i8>* %a, align 16
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%1 = load <16 x i8>* %b, align 16
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%2 = call <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8> %0, <16 x i8> %1)
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ret <16 x i8> %2
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}
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8>, <16 x i8>) #1
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Produces the following code with -mtriple=powerpc64-unknown-linux-gnu:
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# BB#0: # %entry
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addis 3, 2, .LCPI0_0@toc@ha
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addis 4, 2, .LCPI0_1@toc@ha
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addi 3, 3, .LCPI0_0@toc@l
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addi 4, 4, .LCPI0_1@toc@l
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lxvw4x 0, 0, 3
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addi 3, 1, -16
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lxvw4x 35, 0, 4
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stxvw4x 0, 0, 3
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ori 2, 2, 0
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lxvw4x 34, 0, 3
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addi 3, 1, -32
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stxvw4x 35, 0, 3
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vpmsumb 2, 2, 3
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blr
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.long 0
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.quad 0
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The two stxvw4x instructions are not needed.
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With -mtriple=powerpc64le-unknown-linux-gnu, the associated permutes
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are present too.
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//===----------------------------------------------------------------------===//
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The following example is found in test/CodeGen/PowerPC/vec_add_sub_doubleword.ll:
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define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
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275
test/CodeGen/PowerPC/crypto_bifs.ll
Normal file
275
test/CodeGen/PowerPC/crypto_bifs.ll
Normal file
@ -0,0 +1,275 @@
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+crypto < %s | FileCheck %s
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; FIXME: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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; FIXME: The original intent was to add a check-next for the blr after every check.
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; However, this currently fails since we don't eliminate stores of the unused
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; locals. These stores are sometimes scheduled after the crypto instruction
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; Function Attrs: nounwind
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define <16 x i8> @test_vpmsumb() #0 {
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entry:
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%a = alloca <16 x i8>, align 16
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%b = alloca <16 x i8>, align 16
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store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %a, align 16
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store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %b, align 16
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%0 = load <16 x i8>, <16 x i8>* %a, align 16
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%1 = load <16 x i8>, <16 x i8>* %b, align 16
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%2 = call <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8> %0, <16 x i8> %1)
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ret <16 x i8> %2
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; CHECK: vpmsumb 2,
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}
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8>, <16 x i8>) #1
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; Function Attrs: nounwind
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define <8 x i16> @test_vpmsumh() #0 {
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entry:
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%a = alloca <8 x i16>, align 16
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%b = alloca <8 x i16>, align 16
|
||||
store <8 x i16> <i16 258, i16 772, i16 1286, i16 1800, i16 2314, i16 2828, i16 3342, i16 3856>, <8 x i16>* %a, align 16
|
||||
store <8 x i16> <i16 29042, i16 29556, i16 30070, i16 30584, i16 31098, i16 31612, i16 32126, i16 32624>, <8 x i16>* %b, align 16
|
||||
%0 = load <8 x i16>, <8 x i16>* %a, align 16
|
||||
%1 = load <8 x i16>, <8 x i16>* %b, align 16
|
||||
%2 = call <8 x i16> @llvm.ppc.altivec.crypto.vpmsumh(<8 x i16> %0, <8 x i16> %1)
|
||||
ret <8 x i16> %2
|
||||
; CHECK: vpmsumh 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <8 x i16> @llvm.ppc.altivec.crypto.vpmsumh(<8 x i16>, <8 x i16>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <4 x i32> @test_vpmsumw() #0 {
|
||||
entry:
|
||||
%a = alloca <4 x i32>, align 16
|
||||
%b = alloca <4 x i32>, align 16
|
||||
store <4 x i32> <i32 16909060, i32 84281096, i32 151653132, i32 219025168>, <4 x i32>* %a, align 16
|
||||
store <4 x i32> <i32 1903326068, i32 1970698104, i32 2038070140, i32 2105442160>, <4 x i32>* %b, align 16
|
||||
%0 = load <4 x i32>, <4 x i32>* %a, align 16
|
||||
%1 = load <4 x i32>, <4 x i32>* %b, align 16
|
||||
%2 = call <4 x i32> @llvm.ppc.altivec.crypto.vpmsumw(<4 x i32> %0, <4 x i32> %1)
|
||||
ret <4 x i32> %2
|
||||
; CHECK: vpmsumw 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <4 x i32> @llvm.ppc.altivec.crypto.vpmsumw(<4 x i32>, <4 x i32>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <2 x i64> @test_vpmsumd() #0 {
|
||||
entry:
|
||||
%a = alloca <2 x i64>, align 16
|
||||
%b = alloca <2 x i64>, align 16
|
||||
store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
|
||||
store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%2 = call <2 x i64> @llvm.ppc.altivec.crypto.vpmsumd(<2 x i64> %0, <2 x i64> %1)
|
||||
ret <2 x i64> %2
|
||||
; CHECK: vpmsumd 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <2 x i64> @llvm.ppc.altivec.crypto.vpmsumd(<2 x i64>, <2 x i64>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <2 x i64> @test_vsbox() #0 {
|
||||
entry:
|
||||
%a = alloca <2 x i64>, align 16
|
||||
store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = call <2 x i64> @llvm.ppc.altivec.crypto.vsbox(<2 x i64> %0)
|
||||
ret <2 x i64> %1
|
||||
; CHECK: vsbox 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <2 x i64> @llvm.ppc.altivec.crypto.vsbox(<2 x i64>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <16 x i8> @test_vpermxorb() #0 {
|
||||
entry:
|
||||
%a = alloca <16 x i8>, align 16
|
||||
%b = alloca <16 x i8>, align 16
|
||||
%c = alloca <16 x i8>, align 16
|
||||
store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %a, align 16
|
||||
store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %b, align 16
|
||||
store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %c, align 16
|
||||
%0 = load <16 x i8>, <16 x i8>* %a, align 16
|
||||
%1 = load <16 x i8>, <16 x i8>* %b, align 16
|
||||
%2 = load <16 x i8>, <16 x i8>* %c, align 16
|
||||
%3 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
|
||||
ret <16 x i8> %3
|
||||
; CHECK: vpermxor 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8>, <16 x i8>, <16 x i8>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <8 x i16> @test_vpermxorh() #0 {
|
||||
entry:
|
||||
%a = alloca <8 x i16>, align 16
|
||||
%b = alloca <8 x i16>, align 16
|
||||
%c = alloca <8 x i16>, align 16
|
||||
store <8 x i16> <i16 258, i16 772, i16 1286, i16 1800, i16 2314, i16 2828, i16 3342, i16 3856>, <8 x i16>* %a, align 16
|
||||
store <8 x i16> <i16 29042, i16 29556, i16 30070, i16 30584, i16 31098, i16 31612, i16 32126, i16 32624>, <8 x i16>* %b, align 16
|
||||
store <8 x i16> <i16 29042, i16 29556, i16 30070, i16 30584, i16 31098, i16 31612, i16 32126, i16 32624>, <8 x i16>* %c, align 16
|
||||
%0 = load <8 x i16>, <8 x i16>* %a, align 16
|
||||
%1 = bitcast <8 x i16> %0 to <16 x i8>
|
||||
%2 = load <8 x i16>, <8 x i16>* %b, align 16
|
||||
%3 = bitcast <8 x i16> %2 to <16 x i8>
|
||||
%4 = load <8 x i16>, <8 x i16>* %c, align 16
|
||||
%5 = bitcast <8 x i16> %4 to <16 x i8>
|
||||
%6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
|
||||
%7 = bitcast <16 x i8> %6 to <8 x i16>
|
||||
ret <8 x i16> %7
|
||||
; CHECK: vpermxor 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <4 x i32> @test_vpermxorw() #0 {
|
||||
entry:
|
||||
%a = alloca <4 x i32>, align 16
|
||||
%b = alloca <4 x i32>, align 16
|
||||
%c = alloca <4 x i32>, align 16
|
||||
store <4 x i32> <i32 16909060, i32 84281096, i32 151653132, i32 219025168>, <4 x i32>* %a, align 16
|
||||
store <4 x i32> <i32 1903326068, i32 1970698104, i32 2038070140, i32 2105442160>, <4 x i32>* %b, align 16
|
||||
store <4 x i32> <i32 1903326068, i32 1970698104, i32 2038070140, i32 2105442160>, <4 x i32>* %c, align 16
|
||||
%0 = load <4 x i32>, <4 x i32>* %a, align 16
|
||||
%1 = bitcast <4 x i32> %0 to <16 x i8>
|
||||
%2 = load <4 x i32>, <4 x i32>* %b, align 16
|
||||
%3 = bitcast <4 x i32> %2 to <16 x i8>
|
||||
%4 = load <4 x i32>, <4 x i32>* %c, align 16
|
||||
%5 = bitcast <4 x i32> %4 to <16 x i8>
|
||||
%6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
|
||||
%7 = bitcast <16 x i8> %6 to <4 x i32>
|
||||
ret <4 x i32> %7
|
||||
; CHECK: vpermxor 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <2 x i64> @test_vpermxord() #0 {
|
||||
entry:
|
||||
%a = alloca <2 x i64>, align 16
|
||||
%b = alloca <2 x i64>, align 16
|
||||
%c = alloca <2 x i64>, align 16
|
||||
store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
|
||||
store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
|
||||
store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %c, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = bitcast <2 x i64> %0 to <16 x i8>
|
||||
%2 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%3 = bitcast <2 x i64> %2 to <16 x i8>
|
||||
%4 = load <2 x i64>, <2 x i64>* %c, align 16
|
||||
%5 = bitcast <2 x i64> %4 to <16 x i8>
|
||||
%6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
|
||||
%7 = bitcast <16 x i8> %6 to <2 x i64>
|
||||
ret <2 x i64> %7
|
||||
; CHECK: vpermxor 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <2 x i64> @test_vcipher() #0 {
|
||||
entry:
|
||||
%a = alloca <2 x i64>, align 16
|
||||
%b = alloca <2 x i64>, align 16
|
||||
store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
|
||||
store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%2 = call <2 x i64> @llvm.ppc.altivec.crypto.vcipher(<2 x i64> %0, <2 x i64> %1)
|
||||
ret <2 x i64> %2
|
||||
; CHECK: vcipher 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <2 x i64> @llvm.ppc.altivec.crypto.vcipher(<2 x i64>, <2 x i64>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <2 x i64> @test_vcipherlast() #0 {
|
||||
entry:
|
||||
%a = alloca <2 x i64>, align 16
|
||||
%b = alloca <2 x i64>, align 16
|
||||
store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
|
||||
store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%2 = call <2 x i64> @llvm.ppc.altivec.crypto.vcipherlast(<2 x i64> %0, <2 x i64> %1)
|
||||
ret <2 x i64> %2
|
||||
; CHECK: vcipherlast 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <2 x i64> @llvm.ppc.altivec.crypto.vcipherlast(<2 x i64>, <2 x i64>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <2 x i64> @test_vncipher() #0 {
|
||||
entry:
|
||||
%a = alloca <2 x i64>, align 16
|
||||
%b = alloca <2 x i64>, align 16
|
||||
store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
|
||||
store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%2 = call <2 x i64> @llvm.ppc.altivec.crypto.vncipher(<2 x i64> %0, <2 x i64> %1)
|
||||
ret <2 x i64> %2
|
||||
; CHECK: vncipher 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <2 x i64> @llvm.ppc.altivec.crypto.vncipher(<2 x i64>, <2 x i64>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <2 x i64> @test_vncipherlast() #0 {
|
||||
entry:
|
||||
%a = alloca <2 x i64>, align 16
|
||||
%b = alloca <2 x i64>, align 16
|
||||
store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
|
||||
store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%2 = call <2 x i64> @llvm.ppc.altivec.crypto.vncipherlast(<2 x i64> %0, <2 x i64> %1)
|
||||
ret <2 x i64> %2
|
||||
; CHECK: vncipherlast 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <2 x i64> @llvm.ppc.altivec.crypto.vncipherlast(<2 x i64>, <2 x i64>) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <4 x i32> @test_vshasigmaw() #0 {
|
||||
entry:
|
||||
%a = alloca <4 x i32>, align 16
|
||||
store <4 x i32> <i32 16909060, i32 84281096, i32 151653132, i32 219025168>, <4 x i32>* %a, align 16
|
||||
%0 = load <4 x i32>, <4 x i32>* %a, align 16
|
||||
%1 = call <4 x i32> @llvm.ppc.altivec.crypto.vshasigmaw(<4 x i32> %0, i32 1, i32 15)
|
||||
ret <4 x i32> %1
|
||||
; CHECK: vshasigmaw 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <4 x i32> @llvm.ppc.altivec.crypto.vshasigmaw(<4 x i32>, i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define <2 x i64> @test_vshasigmad() #0 {
|
||||
entry:
|
||||
%a = alloca <2 x i64>, align 16
|
||||
store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %a, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = call <2 x i64> @llvm.ppc.altivec.crypto.vshasigmad(<2 x i64> %0, i32 1, i32 15)
|
||||
ret <2 x i64> %1
|
||||
; CHECK: vshasigmad 2,
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <2 x i64> @llvm.ppc.altivec.crypto.vshasigmad(<2 x i64>, i32, i32) #1
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
||||
!llvm.ident = !{!0}
|
||||
|
||||
!0 = !{!"clang version 3.7.0 (trunk 230949) (llvm/trunk 230946)"}
|
||||
@ -120,6 +120,42 @@
|
||||
# CHECK: vperm 2, 3, 4, 5
|
||||
0x10 0x43 0x21 0x6b
|
||||
|
||||
# CHECK: vpermxor 2, 3, 4, 5
|
||||
0x10 0x43 0x21 0x6d
|
||||
|
||||
# CHECK: vsbox 2, 5
|
||||
0x10 0x45 0x05 0xc8
|
||||
|
||||
# CHECK: vcipher 2, 5, 17
|
||||
0x10 0x45 0x8d 0x08
|
||||
|
||||
# CHECK: vcipherlast 2, 5, 17
|
||||
0x10 0x45 0x8d 0x09
|
||||
|
||||
# CHECK: vncipher 2, 5, 17
|
||||
0x10,0x45,0x8d,0x48
|
||||
|
||||
# CHECK: vncipherlast 2, 5, 17
|
||||
0x10,0x45,0x8d,0x49
|
||||
|
||||
# CHECK: vpmsumb 2, 5, 17
|
||||
0x10 0x45 0x8c 0x08
|
||||
|
||||
# CHECK: vpmsumh 2, 5, 17
|
||||
0x10 0x45 0x8c 0x48
|
||||
|
||||
# CHECK: vpmsumw 2, 5, 17
|
||||
0x10 0x45 0x8c 0x88
|
||||
|
||||
# CHECK: vpmsumd 2, 5, 17
|
||||
0x10 0x45 0x8c 0xc8
|
||||
|
||||
# CHECK: vshasigmaw 2, 3, 0, 11
|
||||
0x10 0x43 0x5e 0x82
|
||||
|
||||
# CHECK: vshasigmad 2, 3, 1, 15
|
||||
0x10 0x43 0xfe 0xc2
|
||||
|
||||
# CHECK: vsel 2, 3, 4, 5
|
||||
0x10 0x43 0x21 0x6a
|
||||
|
||||
|
||||
@ -133,6 +133,55 @@
|
||||
# CHECK-BE: vperm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6b]
|
||||
# CHECK-LE: vperm 2, 3, 4, 5 # encoding: [0x6b,0x21,0x43,0x10]
|
||||
vperm 2, 3, 4, 5
|
||||
|
||||
# CHECK-BE: vpermxor 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6d]
|
||||
# CHECK-LE: vpermxor 2, 3, 4, 5 # encoding: [0x6d,0x21,0x43,0x10]
|
||||
vpermxor 2, 3, 4, 5
|
||||
|
||||
# CHECK-BE: vsbox 2, 5 # encoding: [0x10,0x45,0x05,0xc8]
|
||||
# CHECK-LE: vsbox 2, 5 # encoding: [0xc8,0x05,0x45,0x10]
|
||||
vsbox 2, 5
|
||||
|
||||
# CHECK-BE: vcipher 2, 5, 17 # encoding: [0x10,0x45,0x8d,0x08]
|
||||
# CHECK-LE: vcipher 2, 5, 17 # encoding: [0x08,0x8d,0x45,0x10]
|
||||
vcipher 2, 5, 17
|
||||
|
||||
# CHECK-BE: vcipherlast 2, 5, 17 # encoding: [0x10,0x45,0x8d,0x09]
|
||||
# CHECK-LE: vcipherlast 2, 5, 17 # encoding: [0x09,0x8d,0x45,0x10]
|
||||
vcipherlast 2, 5, 17
|
||||
|
||||
# CHECK-BE: vncipher 2, 5, 17 # encoding: [0x10,0x45,0x8d,0x48]
|
||||
# CHECK-LE: vncipher 2, 5, 17 # encoding: [0x48,0x8d,0x45,0x10]
|
||||
vncipher 2, 5, 17
|
||||
|
||||
# CHECK-BE: vncipherlast 2, 5, 17 # encoding: [0x10,0x45,0x8d,0x49]
|
||||
# CHECK-LE: vncipherlast 2, 5, 17 # encoding: [0x49,0x8d,0x45,0x10]
|
||||
vncipherlast 2, 5, 17
|
||||
|
||||
# CHECK-BE: vpmsumb 2, 5, 17 # encoding: [0x10,0x45,0x8c,0x08]
|
||||
# CHECK-LE: vpmsumb 2, 5, 17 # encoding: [0x08,0x8c,0x45,0x10]
|
||||
vpmsumb 2, 5, 17
|
||||
|
||||
# CHECK-BE: vpmsumh 2, 5, 17 # encoding: [0x10,0x45,0x8c,0x48]
|
||||
# CHECK-LE: vpmsumh 2, 5, 17 # encoding: [0x48,0x8c,0x45,0x10]
|
||||
vpmsumh 2, 5, 17
|
||||
|
||||
# CHECK-BE: vpmsumw 2, 5, 17 # encoding: [0x10,0x45,0x8c,0x88]
|
||||
# CHECK-LE: vpmsumw 2, 5, 17 # encoding: [0x88,0x8c,0x45,0x10]
|
||||
vpmsumw 2, 5, 17
|
||||
|
||||
# CHECK-BE: vpmsumd 2, 5, 17 # encoding: [0x10,0x45,0x8c,0xc8]
|
||||
# CHECK-LE: vpmsumd 2, 5, 17 # encoding: [0xc8,0x8c,0x45,0x10]
|
||||
vpmsumd 2, 5, 17
|
||||
|
||||
# CHECK-BE: vshasigmaw 2, 3, 0, 11 # encoding: [0x10,0x43,0x5e,0x82]
|
||||
# CHECK-LE: vshasigmaw 2, 3, 0, 11 # encoding: [0x82,0x5e,0x43,0x10]
|
||||
vshasigmaw 2, 3, 0, 11
|
||||
|
||||
# CHECK-BE: vshasigmad 2, 3, 1, 15 # encoding: [0x10,0x43,0xfe,0xc2]
|
||||
# CHECK-LE: vshasigmad 2, 3, 1, 15 # encoding: [0xc2,0xfe,0x43,0x10]
|
||||
vshasigmad 2, 3, 1, 15
|
||||
|
||||
# CHECK-BE: vsel 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6a]
|
||||
# CHECK-LE: vsel 2, 3, 4, 5 # encoding: [0x6a,0x21,0x43,0x10]
|
||||
vsel 2, 3, 4, 5
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user