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Make it easier to find alpha stuff in doxygen, and fixup labeling
of memory instructions in the assembly, to allow later linking of traces with LLVM Value*s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22271 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
57c24508d3
commit
b69f342b0e
@ -15,6 +15,7 @@
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#include "AlphaRegisterInfo.h"
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#include "llvm/Constants.h" // FIXME: REMOVE
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#include "llvm/Function.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
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#include "llvm/CodeGen/MachineFunction.h"
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@ -443,7 +444,7 @@ namespace {
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/// ISel - Alpha specific code to select Alpha machine instructions for
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/// SelectionDAG operations.
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//===--------------------------------------------------------------------===//
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class ISel : public SelectionDAGISel {
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class AlphaISel : public SelectionDAGISel {
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/// AlphaLowering - This object fully describes how to lower LLVM code to an
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/// Alpha-specific SelectionDAG.
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@ -468,7 +469,7 @@ class ISel : public SelectionDAGISel {
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int max_depth;
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public:
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ISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
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AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
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{}
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/// InstructionSelectBasicBlock - This callback is invoked by
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@ -519,7 +520,7 @@ public:
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};
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}
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void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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void AlphaISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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// If this function has live-in values, emit the copies from pregs to vregs at
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// the top of the function, before anything else.
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MachineBasicBlock *BB = MF.begin();
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@ -542,8 +543,9 @@ void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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//Find the offset of the arg in it's parent's function
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static int getValueOffset(const Value* v)
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{
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static int uniqneg = -1;
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if (v == NULL)
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return 0;
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return uniqneg--;
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const Instruction* itarget = dyn_cast<Instruction>(v);
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const BasicBlock* btarget = itarget->getParent();
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@ -559,6 +561,24 @@ static int getValueOffset(const Value* v)
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return i;
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}
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//Find the offset of the function in it's module
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static int getFunctionOffset(const Function* fun)
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{
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const Module* M = fun->getParent();
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//offset due to earlier BBs
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int i = 0;
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for(Module::const_iterator ii = M->begin(); &*ii != fun; ++ii)
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++i;
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return i;
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}
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static int getUID()
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{
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static int id = 0;
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return ++id;
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}
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//Factorize a number using the list of constants
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static bool factorize(int v[], int res[], int size, uint64_t c)
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@ -680,7 +700,7 @@ static struct mu magicu(uint64_t d)
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/// return a DAG expression to select that will generate the same value by
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/// multiplying by a magic number. See:
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/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
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SDOperand ISel::BuildSDIVSequence(SDOperand N) {
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SDOperand AlphaISel::BuildSDIVSequence(SDOperand N) {
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int64_t d = (int64_t)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
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ms magics = magic(d);
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// Multiply the numerator (operand 0) by the magic value
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@ -706,7 +726,7 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
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/// return a DAG expression to select that will generate the same value by
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/// multiplying by a magic number. See:
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/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
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SDOperand ISel::BuildUDIVSequence(SDOperand N) {
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SDOperand AlphaISel::BuildUDIVSequence(SDOperand N) {
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unsigned d =
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(unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
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mu magics = magicu(d);
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@ -781,7 +801,7 @@ static unsigned GetSymVersion(unsigned opcode)
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}
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}
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void ISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
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void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
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{
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unsigned Opc;
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if (EnableAlphaFTOI) {
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@ -801,7 +821,7 @@ void ISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
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}
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}
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void ISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
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void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
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{
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unsigned Opc;
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if (EnableAlphaFTOI) {
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@ -821,7 +841,7 @@ void ISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
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}
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}
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bool ISel::SelectFPSetCC(SDOperand N, unsigned dst)
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bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
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{
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SDNode *Node = N.Val;
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unsigned Opc, Tmp1, Tmp2, Tmp3;
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@ -880,7 +900,7 @@ bool ISel::SelectFPSetCC(SDOperand N, unsigned dst)
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}
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//Check to see if the load is a constant offset from a base register
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void ISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
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void AlphaISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
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{
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unsigned opcode = N.getOpcode();
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if (opcode == ISD::ADD) {
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@ -904,7 +924,7 @@ void ISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
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return;
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}
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void ISel::SelectBranchCC(SDOperand N)
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void AlphaISel::SelectBranchCC(SDOperand N)
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{
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assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
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MachineBasicBlock *Dest =
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@ -1015,7 +1035,7 @@ void ISel::SelectBranchCC(SDOperand N)
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abort(); //Should never be reached
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}
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unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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unsigned AlphaISel::SelectExprFP(SDOperand N, unsigned Result)
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{
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unsigned Tmp1, Tmp2, Tmp3;
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unsigned Opc = 0;
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@ -1168,7 +1188,8 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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if (EnableAlphaLSMark)
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{
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int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
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BuildMI(BB, Alpha::MEMLABEL, 2).addImm(i);
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int j = getFunctionOffset(BB->getParent()->getFunction());
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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}
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if (Address.getOpcode() == ISD::GlobalAddress) {
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@ -1318,7 +1339,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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return 0;
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}
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unsigned ISel::SelectExpr(SDOperand N) {
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unsigned AlphaISel::SelectExpr(SDOperand N) {
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unsigned Result;
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unsigned Tmp1, Tmp2 = 0, Tmp3;
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unsigned Opc = 0;
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@ -1482,6 +1503,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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}
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if (EnableAlphaLSMark)
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{
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int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
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int j = getFunctionOffset(BB->getParent()->getFunction());
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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}
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if (Address.getOpcode() == ISD::GlobalAddress) {
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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@ -2231,7 +2259,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return 0;
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}
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void ISel::Select(SDOperand N) {
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void AlphaISel::Select(SDOperand N) {
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unsigned Tmp1, Tmp2, Opc;
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unsigned opcode = N.getOpcode();
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@ -2353,6 +2381,13 @@ void ISel::Select(SDOperand N) {
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}
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}
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if (EnableAlphaLSMark)
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{
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int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue());
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int j = getFunctionOffset(BB->getParent()->getFunction());
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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}
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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AlphaLowering.restoreGP(BB);
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@ -2411,6 +2446,6 @@ void ISel::Select(SDOperand N) {
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/// description file.
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///
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FunctionPass *llvm::createAlphaPatternInstructionSelector(TargetMachine &TM) {
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return new ISel(TM);
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return new AlphaISel(TM);
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}
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@ -31,7 +31,7 @@ def ADJUSTSTACKUP : PseudoInstAlpha<(ops ), "ADJUP">;
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def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops ), "ADJDOWN">;
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def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n">;
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def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n">;
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def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i), "LSMARKER_$i:\n">;
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def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k), "LSMARKER$$$i$$$j$$$k:\n">;
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//*****************
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//These are shortcuts, the assembler expands them
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