From b71bcdb26cfb0d07309cdd03a3d8549e7765d552 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Thu, 29 Aug 2019 14:46:49 +0000 Subject: [PATCH] [NFC][SimplifyCFG] 'Safely extract low bits' pattern will also benefit from -phi-node-folding-threshold=3 This is the naive implementation of x86 BZHI/BEXTR instruction: it takes input and bit count, and extracts low nbits up to bit width. I.e. unlike shift it does not have any UB when nbits >= bitwidth. Which means we don't need a while PHI here, simple select will do. And if it's a select, it should then be trivial to fix codegen to select it to BEXTR/BZHI. See https://bugs.llvm.org/show_bug.cgi?id=34704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370369 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../SimplifyCFG/safe-low-bit-extract.ll | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 test/Transforms/SimplifyCFG/safe-low-bit-extract.ll diff --git a/test/Transforms/SimplifyCFG/safe-low-bit-extract.ll b/test/Transforms/SimplifyCFG/safe-low-bit-extract.ll new file mode 100644 index 00000000000..354cfff7ba7 --- /dev/null +++ b/test/Transforms/SimplifyCFG/safe-low-bit-extract.ll @@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -simplifycfg -S | FileCheck %s + +; This is the naive implementation of x86 BZHI/BEXTR instruction: +; it takes input and bit count, and extracts low nbits up to bit width. +; I.e. unlike shift it does not have any UB when nbits >= bitwidth. +; Which means we don't need a while PHI here, simple select will do. +define i32 @extract_low_bits(i32 %input, i32 %nbits) { +; CHECK-LABEL: @extract_low_bits( +; CHECK-NEXT: begin: +; CHECK-NEXT: [[SHOULD_MASK:%.*]] = icmp ult i32 [[NBITS:%.*]], 32 +; CHECK-NEXT: br i1 [[SHOULD_MASK]], label [[PERFORM_MASKING:%.*]], label [[END:%.*]] +; CHECK: perform_masking: +; CHECK-NEXT: [[MASK_NOT:%.*]] = shl nsw i32 -1, [[NBITS]] +; CHECK-NEXT: [[MASK:%.*]] = xor i32 [[MASK_NOT]], -1 +; CHECK-NEXT: [[MASKED:%.*]] = and i32 [[MASK]], [[INPUT:%.*]] +; CHECK-NEXT: br label [[END]] +; CHECK: end: +; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[MASKED]], [[PERFORM_MASKING]] ], [ [[INPUT]], [[BEGIN:%.*]] ] +; CHECK-NEXT: ret i32 [[RES]] +; +begin: + %should_mask = icmp ult i32 %nbits, 32 + br i1 %should_mask, label %perform_masking, label %end + +perform_masking: ; preds = %begin + %mask.not = shl nsw i32 -1, %nbits + %mask = xor i32 %mask.not, -1 + %masked = and i32 %mask, %input + br label %end + +end: ; preds = %perform_masking, %begin + %res = phi i32 [ %masked, %perform_masking ], [ %input, %begin ] + ret i32 %res +}