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ARM case-insensitive checking for APSR_nzcv.
rdar://11056591 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1198,7 +1198,7 @@ class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
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// to APSR.
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let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
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def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
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"vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>;
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"vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
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// Application level FPSCR -> GPR
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let hasSideEffects = 1, Uses = [FPSCR] in
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@ -3258,7 +3258,8 @@ parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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if (isMClass()) {
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// See ARMv6-M 10.1.1
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unsigned FlagsVal = StringSwitch<unsigned>(Mask)
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std::string Name = Mask.lower();
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unsigned FlagsVal = StringSwitch<unsigned>(Name)
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.Case("apsr", 0)
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.Case("iapsr", 1)
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.Case("eapsr", 2)
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@ -4432,10 +4433,11 @@ bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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else if (Res == -1) // irrecoverable error
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return true;
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// If this is VMRS, check for the apsr_nzcv operand.
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if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
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if (Mnemonic == "vmrs" &&
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Parser.getTok().getString().equals_lower("apsr_nzcv")) {
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S = Parser.getTok().getLoc();
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Parser.Lex();
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Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
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Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
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return false;
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}
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23
lib/Target/ARM/AsmParser/x
Normal file
23
lib/Target/ARM/AsmParser/x
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@ -0,0 +1,23 @@
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diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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index af973e8..cbdae2a 100644
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--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -3254,7 +3254,8 @@ parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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- StringRef Mask = Tok.getString();
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+ std::string MaskStr = Tok.getString().lower();
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+ StringRef Mask = MaskStr; // convenience for slice() and such.
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if (isMClass()) {
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// See ARMv6-M 10.1.1
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@@ -3290,7 +3291,7 @@ parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
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size_t Start = 0, Next = Mask.find('_');
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StringRef Flags = "";
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- std::string SpecReg = Mask.slice(Start, Next).lower();
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+ StringRef SpecReg = Mask.slice(Start, Next);
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if (Next != StringRef::npos)
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Flags = Mask.slice(Next+1, Mask.size());
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@ -9,7 +9,7 @@ entry:
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; CHECK: vldr [[S0:s[0-9]+]],
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; CHECK: vldr [[S1:s[0-9]+]],
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; CHECK: vcmpe.f32 [[S1]], [[S0]]
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; CHECK: vmrs apsr_nzcv, fpscr
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; CHECK: vmrs APSR_nzcv, fpscr
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; CHECK: beq
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%0 = load float* %a
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%1 = load float* %b
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@ -5,7 +5,7 @@ define i32 @f7(float %a, float %b) {
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entry:
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; CHECK: f7:
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; CHECK: vcmpe.f32
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; CHECK: vmrs apsr_nzcv, fpscr
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; CHECK: vmrs APSR_nzcv, fpscr
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; CHECK: movweq
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; CHECK-NOT: vmrs
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; CHECK: movwvs
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@ -18,7 +18,7 @@ bb.nph: ; preds = %entry
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bb: ; preds = %bb4, %bb.nph
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; CHECK: vcmpe.f64
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; CHECK: vmrs apsr_nzcv, fpscr
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; CHECK: vmrs APSR_nzcv, fpscr
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%r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ]
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%n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ]
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%scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0
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@ -33,7 +33,7 @@ bb1: ; preds = %bb
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; CHECK-NOT: vcmpemi
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; CHECK-NOT: vmrsmi
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; CHECK: vcmpe.f64
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; CHECK: vmrs apsr_nzcv, fpscr
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; CHECK: vmrs APSR_nzcv, fpscr
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%scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2
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%6 = load double* %scevgep12, align 4
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%7 = fcmp uge double %3, %6
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@ -120,8 +120,10 @@
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@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
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vnmls.f32 s1, s2, s0
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@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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vmrs APSR_nzcv, fpscr
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vmrs apsr_nzcv, fpscr
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fmstat
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