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https://github.com/RPCS3/llvm.git
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Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
120119da13
commit
b97aec663b
include/llvm/Target
lib
CodeGen
Target
ARM
Alpha
IA64
Mips
PowerPC
Sparc
X86
utils/TableGen
@ -677,8 +677,10 @@ public:
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/// Debug information queries.
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/// Debug information queries.
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/// getDwarfRegNum - Map a target register to an equivalent dwarf register
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/// getDwarfRegNum - Map a target register to an equivalent dwarf register
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/// number. Returns -1 if there is no equivalent value.
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/// number. Returns -1 if there is no equivalent value. The second
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virtual int getDwarfRegNum(unsigned RegNum) const = 0;
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/// parameter allows targets to use different numberings for EH info and
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/// deubgging info.
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virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
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/// getFrameRegister - This method should return the register used as a base
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/// getFrameRegister - This method should return the register used as a base
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/// for values allocated in the current stack frame.
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/// for values allocated in the current stack frame.
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@ -968,7 +968,7 @@ public:
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/// EmitFrameMoves - Emit frame instructions to describe the layout of the
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/// EmitFrameMoves - Emit frame instructions to describe the layout of the
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/// frame.
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/// frame.
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void EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID,
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void EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID,
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const std::vector<MachineMove> &Moves) {
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const std::vector<MachineMove> &Moves, bool isEH) {
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int stackGrowth =
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int stackGrowth =
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Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
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Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
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TargetFrameInfo::StackGrowsUp ?
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TargetFrameInfo::StackGrowsUp ?
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@ -1010,7 +1010,7 @@ public:
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} else {
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} else {
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Asm->EmitInt8(DW_CFA_def_cfa);
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Asm->EmitInt8(DW_CFA_def_cfa);
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Asm->EOL("DW_CFA_def_cfa");
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Asm->EOL("DW_CFA_def_cfa");
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Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister()));
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Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister(), isEH));
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Asm->EOL("Register");
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Asm->EOL("Register");
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}
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}
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@ -1026,13 +1026,13 @@ public:
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if (Dst.isRegister()) {
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if (Dst.isRegister()) {
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Asm->EmitInt8(DW_CFA_def_cfa_register);
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Asm->EmitInt8(DW_CFA_def_cfa_register);
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Asm->EOL("DW_CFA_def_cfa_register");
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Asm->EOL("DW_CFA_def_cfa_register");
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Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister()));
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Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister(), isEH));
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Asm->EOL("Register");
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Asm->EOL("Register");
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} else {
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} else {
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assert(0 && "Machine move no supported yet.");
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assert(0 && "Machine move no supported yet.");
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}
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}
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} else {
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} else {
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unsigned Reg = RI->getDwarfRegNum(Src.getRegister());
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unsigned Reg = RI->getDwarfRegNum(Src.getRegister(), isEH);
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int Offset = Dst.getOffset() / stackGrowth;
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int Offset = Dst.getOffset() / stackGrowth;
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if (Offset < 0) {
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if (Offset < 0) {
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@ -1340,7 +1340,7 @@ private:
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/// provided.
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/// provided.
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void AddAddress(DIE *Die, unsigned Attribute,
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void AddAddress(DIE *Die, unsigned Attribute,
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const MachineLocation &Location) {
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const MachineLocation &Location) {
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unsigned Reg = RI->getDwarfRegNum(Location.getRegister());
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unsigned Reg = RI->getDwarfRegNum(Location.getRegister(), false);
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DIEBlock *Block = new DIEBlock();
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DIEBlock *Block = new DIEBlock();
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if (Location.isRegister()) {
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if (Location.isRegister()) {
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@ -2370,13 +2370,13 @@ private:
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Asm->EOL("CIE Code Alignment Factor");
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Asm->EOL("CIE Code Alignment Factor");
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Asm->EmitSLEB128Bytes(stackGrowth);
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Asm->EmitSLEB128Bytes(stackGrowth);
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Asm->EOL("CIE Data Alignment Factor");
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Asm->EOL("CIE Data Alignment Factor");
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Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister()));
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Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), false));
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Asm->EOL("CIE RA Column");
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Asm->EOL("CIE RA Column");
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std::vector<MachineMove> Moves;
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std::vector<MachineMove> Moves;
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RI->getInitialFrameState(Moves);
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RI->getInitialFrameState(Moves);
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EmitFrameMoves(NULL, 0, Moves);
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EmitFrameMoves(NULL, 0, Moves, false);
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Asm->EmitAlignment(2);
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Asm->EmitAlignment(2);
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EmitLabel("debug_frame_common_end", 0);
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EmitLabel("debug_frame_common_end", 0);
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@ -2409,7 +2409,7 @@ private:
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"func_begin", DebugFrameInfo.Number);
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"func_begin", DebugFrameInfo.Number);
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Asm->EOL("FDE address range");
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Asm->EOL("FDE address range");
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EmitFrameMoves("func_begin", DebugFrameInfo.Number, DebugFrameInfo.Moves);
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EmitFrameMoves("func_begin", DebugFrameInfo.Number, DebugFrameInfo.Moves, false);
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Asm->EmitAlignment(2);
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Asm->EmitAlignment(2);
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EmitLabel("debug_frame_end", DebugFrameInfo.Number);
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EmitLabel("debug_frame_end", DebugFrameInfo.Number);
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@ -2817,7 +2817,7 @@ private:
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Asm->EOL("CIE Code Alignment Factor");
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Asm->EOL("CIE Code Alignment Factor");
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Asm->EmitSLEB128Bytes(stackGrowth);
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Asm->EmitSLEB128Bytes(stackGrowth);
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Asm->EOL("CIE Data Alignment Factor");
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Asm->EOL("CIE Data Alignment Factor");
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Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister()));
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Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), true));
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Asm->EOL("CIE RA Column");
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Asm->EOL("CIE RA Column");
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// If there is a personality, we need to indicate the functions location.
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// If there is a personality, we need to indicate the functions location.
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@ -2853,7 +2853,7 @@ private:
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// Indicate locations of general callee saved registers in frame.
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// Indicate locations of general callee saved registers in frame.
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std::vector<MachineMove> Moves;
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std::vector<MachineMove> Moves;
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RI->getInitialFrameState(Moves);
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RI->getInitialFrameState(Moves);
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EmitFrameMoves(NULL, 0, Moves);
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EmitFrameMoves(NULL, 0, Moves, true);
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Asm->EmitAlignment(2);
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Asm->EmitAlignment(2);
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EmitLabel("eh_frame_common_end", Index);
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EmitLabel("eh_frame_common_end", Index);
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@ -2915,7 +2915,7 @@ private:
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// Indicate locations of function specific callee saved registers in
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// Indicate locations of function specific callee saved registers in
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// frame.
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// frame.
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EmitFrameMoves("eh_func_begin", EHFrameInfo.Number, EHFrameInfo.Moves);
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EmitFrameMoves("eh_func_begin", EHFrameInfo.Number, EHFrameInfo.Moves, true);
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Asm->EmitAlignment(2);
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Asm->EmitAlignment(2);
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EmitLabel("eh_frame_end", EHFrameInfo.Number);
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EmitLabel("eh_frame_end", EHFrameInfo.Number);
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@ -1660,7 +1660,7 @@ unsigned ARMRegisterInfo::getEHHandlerRegister() const {
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return 0;
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return 0;
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}
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}
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int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
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int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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assert(0 && "What is the dwarf register number");
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assert(0 && "What is the dwarf register number");
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return -1;
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return -1;
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}
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}
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@ -118,7 +118,7 @@ public:
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unsigned getEHExceptionRegister() const;
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum) const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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};
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};
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} // end namespace llvm
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} // end namespace llvm
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@ -480,7 +480,7 @@ unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
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return 0;
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return 0;
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}
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}
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int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
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int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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assert(0 && "What is the dwarf register number");
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assert(0 && "What is the dwarf register number");
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return -1;
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return -1;
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}
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}
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@ -93,7 +93,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
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unsigned getEHExceptionRegister() const;
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum) const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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static std::string getPrettyName(unsigned reg);
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static std::string getPrettyName(unsigned reg);
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};
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};
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@ -451,7 +451,7 @@ unsigned IA64RegisterInfo::getEHHandlerRegister() const {
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return 0;
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return 0;
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}
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}
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int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum) const {
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int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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assert(0 && "What is the dwarf register number");
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assert(0 && "What is the dwarf register number");
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return -1;
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return -1;
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}
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}
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@ -85,7 +85,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
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unsigned getEHExceptionRegister() const;
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum) const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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};
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};
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} // End llvm namespace
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} // End llvm namespace
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@ -539,7 +539,7 @@ getEHHandlerRegister() const {
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}
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}
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int MipsRegisterInfo::
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int MipsRegisterInfo::
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getDwarfRegNum(unsigned RegNum) const {
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getDwarfRegNum(unsigned RegNum, bool isEH) const {
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assert(0 && "What is the dwarf register number");
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assert(0 && "What is the dwarf register number");
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return -1;
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return -1;
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}
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}
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@ -97,7 +97,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
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unsigned getEHExceptionRegister() const;
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum) const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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};
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};
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} // end namespace llvm
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} // end namespace llvm
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@ -1277,7 +1277,7 @@ unsigned PPCRegisterInfo::getEHHandlerRegister() const {
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return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
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return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
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}
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}
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int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
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int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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// FIXME: Most probably dwarf numbers differs for Linux and Darwin
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// FIXME: Most probably dwarf numbers differs for Linux and Darwin
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return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
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return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
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}
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}
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@ -117,7 +117,7 @@ public:
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unsigned getEHExceptionRegister() const;
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum) const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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};
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};
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} // end namespace llvm
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} // end namespace llvm
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@ -58,7 +58,7 @@ DarwinTargetAsmInfo::DarwinTargetAsmInfo(const PPCTargetMachine &TM)
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UsedDirective = "\t.no_dead_strip\t";
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UsedDirective = "\t.no_dead_strip\t";
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WeakRefDirective = "\t.weak_reference\t";
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WeakRefDirective = "\t.weak_reference\t";
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HiddenDirective = "\t.private_extern\t";
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HiddenDirective = "\t.private_extern\t";
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SupportsExceptionHandling = false;
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SupportsExceptionHandling = true;
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NeedsIndirectEncoding = true;
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NeedsIndirectEncoding = true;
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BSSSection = 0;
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BSSSection = 0;
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@ -333,7 +333,7 @@ unsigned SparcRegisterInfo::getEHHandlerRegister() const {
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return 0;
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return 0;
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}
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}
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int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
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int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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assert(0 && "What is the dwarf register number");
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assert(0 && "What is the dwarf register number");
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return -1;
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return -1;
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}
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}
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@ -97,7 +97,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
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unsigned getEHExceptionRegister() const;
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum) const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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};
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};
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} // end namespace llvm
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} // end namespace llvm
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@ -384,7 +384,6 @@ static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
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/// e.g. r8, xmm8, etc.
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/// e.g. r8, xmm8, etc.
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bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
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bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
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if (!MO.isRegister()) return false;
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if (!MO.isRegister()) return false;
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unsigned RegNo = MO.getReg();
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switch (MO.getReg()) {
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switch (MO.getReg()) {
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default: break;
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default: break;
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case X86::R8: case X86::R9: case X86::R10: case X86::R11:
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case X86::R8: case X86::R9: case X86::R10: case X86::R11:
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@ -657,7 +657,7 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
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// getDwarfRegNum - This function maps LLVM register identifiers to the
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// getDwarfRegNum - This function maps LLVM register identifiers to the
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// Dwarf specific numbering, used in debug info and exception tables.
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// Dwarf specific numbering, used in debug info and exception tables.
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int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const {
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int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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unsigned Flavour = DWARFFlavour::X86_64;
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unsigned Flavour = DWARFFlavour::X86_64;
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if (!Subtarget->is64Bit()) {
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if (!Subtarget->is64Bit()) {
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@ -87,7 +87,7 @@ public:
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/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
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/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
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/// (created by TableGen) for target dependencies.
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/// (created by TableGen) for target dependencies.
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int getDwarfRegNum(unsigned RegNum) const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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/// Code Generation virtual methods...
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/// Code Generation virtual methods...
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///
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///
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@ -101,8 +101,7 @@ X86TargetAsmInfo::X86TargetAsmInfo(const X86TargetMachine &TM) {
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DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug";
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DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug";
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// Exceptions handling
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// Exceptions handling
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if (!Subtarget->is64Bit())
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SupportsExceptionHandling = true;
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SupportsExceptionHandling = true;
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AbsoluteEHSectionOffsets = false;
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AbsoluteEHSectionOffsets = false;
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DwarfEHFrameSection =
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DwarfEHFrameSection =
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".section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support";
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".section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support";
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@ -62,7 +62,7 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) {
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<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
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<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
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<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
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<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
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<< "unsigned Flavour) const;\n"
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<< "unsigned Flavour) const;\n"
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<< " virtual int getDwarfRegNum(unsigned RegNum) const = 0;\n"
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<< " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
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<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
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<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
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<< "};\n\n";
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<< "};\n\n";
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