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Add parameter to getDwarfRegNum to permit targets

to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2007-11-13 19:13:01 +00:00
parent 120119da13
commit b97aec663b
20 changed files with 32 additions and 32 deletions

@ -677,8 +677,10 @@ public:
/// Debug information queries. /// Debug information queries.
/// getDwarfRegNum - Map a target register to an equivalent dwarf register /// getDwarfRegNum - Map a target register to an equivalent dwarf register
/// number. Returns -1 if there is no equivalent value. /// number. Returns -1 if there is no equivalent value. The second
virtual int getDwarfRegNum(unsigned RegNum) const = 0; /// parameter allows targets to use different numberings for EH info and
/// deubgging info.
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
/// getFrameRegister - This method should return the register used as a base /// getFrameRegister - This method should return the register used as a base
/// for values allocated in the current stack frame. /// for values allocated in the current stack frame.

@ -968,7 +968,7 @@ public:
/// EmitFrameMoves - Emit frame instructions to describe the layout of the /// EmitFrameMoves - Emit frame instructions to describe the layout of the
/// frame. /// frame.
void EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID, void EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID,
const std::vector<MachineMove> &Moves) { const std::vector<MachineMove> &Moves, bool isEH) {
int stackGrowth = int stackGrowth =
Asm->TM.getFrameInfo()->getStackGrowthDirection() == Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
TargetFrameInfo::StackGrowsUp ? TargetFrameInfo::StackGrowsUp ?
@ -1010,7 +1010,7 @@ public:
} else { } else {
Asm->EmitInt8(DW_CFA_def_cfa); Asm->EmitInt8(DW_CFA_def_cfa);
Asm->EOL("DW_CFA_def_cfa"); Asm->EOL("DW_CFA_def_cfa");
Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister())); Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister(), isEH));
Asm->EOL("Register"); Asm->EOL("Register");
} }
@ -1026,13 +1026,13 @@ public:
if (Dst.isRegister()) { if (Dst.isRegister()) {
Asm->EmitInt8(DW_CFA_def_cfa_register); Asm->EmitInt8(DW_CFA_def_cfa_register);
Asm->EOL("DW_CFA_def_cfa_register"); Asm->EOL("DW_CFA_def_cfa_register");
Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister())); Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister(), isEH));
Asm->EOL("Register"); Asm->EOL("Register");
} else { } else {
assert(0 && "Machine move no supported yet."); assert(0 && "Machine move no supported yet.");
} }
} else { } else {
unsigned Reg = RI->getDwarfRegNum(Src.getRegister()); unsigned Reg = RI->getDwarfRegNum(Src.getRegister(), isEH);
int Offset = Dst.getOffset() / stackGrowth; int Offset = Dst.getOffset() / stackGrowth;
if (Offset < 0) { if (Offset < 0) {
@ -1340,7 +1340,7 @@ private:
/// provided. /// provided.
void AddAddress(DIE *Die, unsigned Attribute, void AddAddress(DIE *Die, unsigned Attribute,
const MachineLocation &Location) { const MachineLocation &Location) {
unsigned Reg = RI->getDwarfRegNum(Location.getRegister()); unsigned Reg = RI->getDwarfRegNum(Location.getRegister(), false);
DIEBlock *Block = new DIEBlock(); DIEBlock *Block = new DIEBlock();
if (Location.isRegister()) { if (Location.isRegister()) {
@ -2370,13 +2370,13 @@ private:
Asm->EOL("CIE Code Alignment Factor"); Asm->EOL("CIE Code Alignment Factor");
Asm->EmitSLEB128Bytes(stackGrowth); Asm->EmitSLEB128Bytes(stackGrowth);
Asm->EOL("CIE Data Alignment Factor"); Asm->EOL("CIE Data Alignment Factor");
Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister())); Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), false));
Asm->EOL("CIE RA Column"); Asm->EOL("CIE RA Column");
std::vector<MachineMove> Moves; std::vector<MachineMove> Moves;
RI->getInitialFrameState(Moves); RI->getInitialFrameState(Moves);
EmitFrameMoves(NULL, 0, Moves); EmitFrameMoves(NULL, 0, Moves, false);
Asm->EmitAlignment(2); Asm->EmitAlignment(2);
EmitLabel("debug_frame_common_end", 0); EmitLabel("debug_frame_common_end", 0);
@ -2409,7 +2409,7 @@ private:
"func_begin", DebugFrameInfo.Number); "func_begin", DebugFrameInfo.Number);
Asm->EOL("FDE address range"); Asm->EOL("FDE address range");
EmitFrameMoves("func_begin", DebugFrameInfo.Number, DebugFrameInfo.Moves); EmitFrameMoves("func_begin", DebugFrameInfo.Number, DebugFrameInfo.Moves, false);
Asm->EmitAlignment(2); Asm->EmitAlignment(2);
EmitLabel("debug_frame_end", DebugFrameInfo.Number); EmitLabel("debug_frame_end", DebugFrameInfo.Number);
@ -2817,7 +2817,7 @@ private:
Asm->EOL("CIE Code Alignment Factor"); Asm->EOL("CIE Code Alignment Factor");
Asm->EmitSLEB128Bytes(stackGrowth); Asm->EmitSLEB128Bytes(stackGrowth);
Asm->EOL("CIE Data Alignment Factor"); Asm->EOL("CIE Data Alignment Factor");
Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister())); Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), true));
Asm->EOL("CIE RA Column"); Asm->EOL("CIE RA Column");
// If there is a personality, we need to indicate the functions location. // If there is a personality, we need to indicate the functions location.
@ -2853,7 +2853,7 @@ private:
// Indicate locations of general callee saved registers in frame. // Indicate locations of general callee saved registers in frame.
std::vector<MachineMove> Moves; std::vector<MachineMove> Moves;
RI->getInitialFrameState(Moves); RI->getInitialFrameState(Moves);
EmitFrameMoves(NULL, 0, Moves); EmitFrameMoves(NULL, 0, Moves, true);
Asm->EmitAlignment(2); Asm->EmitAlignment(2);
EmitLabel("eh_frame_common_end", Index); EmitLabel("eh_frame_common_end", Index);
@ -2915,7 +2915,7 @@ private:
// Indicate locations of function specific callee saved registers in // Indicate locations of function specific callee saved registers in
// frame. // frame.
EmitFrameMoves("eh_func_begin", EHFrameInfo.Number, EHFrameInfo.Moves); EmitFrameMoves("eh_func_begin", EHFrameInfo.Number, EHFrameInfo.Moves, true);
Asm->EmitAlignment(2); Asm->EmitAlignment(2);
EmitLabel("eh_frame_end", EHFrameInfo.Number); EmitLabel("eh_frame_end", EHFrameInfo.Number);

@ -1660,7 +1660,7 @@ unsigned ARMRegisterInfo::getEHHandlerRegister() const {
return 0; return 0;
} }
int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum) const { int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number"); assert(0 && "What is the dwarf register number");
return -1; return -1;
} }

@ -118,7 +118,7 @@ public:
unsigned getEHExceptionRegister() const; unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const; unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum) const; int getDwarfRegNum(unsigned RegNum, bool isEH) const;
}; };
} // end namespace llvm } // end namespace llvm

@ -480,7 +480,7 @@ unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
return 0; return 0;
} }
int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum) const { int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number"); assert(0 && "What is the dwarf register number");
return -1; return -1;
} }

@ -93,7 +93,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
unsigned getEHExceptionRegister() const; unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const; unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum) const; int getDwarfRegNum(unsigned RegNum, bool isEH) const;
static std::string getPrettyName(unsigned reg); static std::string getPrettyName(unsigned reg);
}; };

@ -451,7 +451,7 @@ unsigned IA64RegisterInfo::getEHHandlerRegister() const {
return 0; return 0;
} }
int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum) const { int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number"); assert(0 && "What is the dwarf register number");
return -1; return -1;
} }

@ -85,7 +85,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
unsigned getEHExceptionRegister() const; unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const; unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum) const; int getDwarfRegNum(unsigned RegNum, bool isEH) const;
}; };
} // End llvm namespace } // End llvm namespace

@ -539,7 +539,7 @@ getEHHandlerRegister() const {
} }
int MipsRegisterInfo:: int MipsRegisterInfo::
getDwarfRegNum(unsigned RegNum) const { getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number"); assert(0 && "What is the dwarf register number");
return -1; return -1;
} }

@ -97,7 +97,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
unsigned getEHExceptionRegister() const; unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const; unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum) const; int getDwarfRegNum(unsigned RegNum, bool isEH) const;
}; };
} // end namespace llvm } // end namespace llvm

@ -1277,7 +1277,7 @@ unsigned PPCRegisterInfo::getEHHandlerRegister() const {
return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
} }
int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum) const { int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
// FIXME: Most probably dwarf numbers differs for Linux and Darwin // FIXME: Most probably dwarf numbers differs for Linux and Darwin
return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
} }

@ -117,7 +117,7 @@ public:
unsigned getEHExceptionRegister() const; unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const; unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum) const; int getDwarfRegNum(unsigned RegNum, bool isEH) const;
}; };
} // end namespace llvm } // end namespace llvm

@ -58,7 +58,7 @@ DarwinTargetAsmInfo::DarwinTargetAsmInfo(const PPCTargetMachine &TM)
UsedDirective = "\t.no_dead_strip\t"; UsedDirective = "\t.no_dead_strip\t";
WeakRefDirective = "\t.weak_reference\t"; WeakRefDirective = "\t.weak_reference\t";
HiddenDirective = "\t.private_extern\t"; HiddenDirective = "\t.private_extern\t";
SupportsExceptionHandling = false; SupportsExceptionHandling = true;
NeedsIndirectEncoding = true; NeedsIndirectEncoding = true;
BSSSection = 0; BSSSection = 0;

@ -333,7 +333,7 @@ unsigned SparcRegisterInfo::getEHHandlerRegister() const {
return 0; return 0;
} }
int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum) const { int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number"); assert(0 && "What is the dwarf register number");
return -1; return -1;
} }

@ -97,7 +97,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
unsigned getEHExceptionRegister() const; unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const; unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum) const; int getDwarfRegNum(unsigned RegNum, bool isEH) const;
}; };
} // end namespace llvm } // end namespace llvm

@ -384,7 +384,6 @@ static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
/// e.g. r8, xmm8, etc. /// e.g. r8, xmm8, etc.
bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) { bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
if (!MO.isRegister()) return false; if (!MO.isRegister()) return false;
unsigned RegNo = MO.getReg();
switch (MO.getReg()) { switch (MO.getReg()) {
default: break; default: break;
case X86::R8: case X86::R9: case X86::R10: case X86::R11: case X86::R8: case X86::R9: case X86::R10: case X86::R11:

@ -657,7 +657,7 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
// getDwarfRegNum - This function maps LLVM register identifiers to the // getDwarfRegNum - This function maps LLVM register identifiers to the
// Dwarf specific numbering, used in debug info and exception tables. // Dwarf specific numbering, used in debug info and exception tables.
int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const { int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
unsigned Flavour = DWARFFlavour::X86_64; unsigned Flavour = DWARFFlavour::X86_64;
if (!Subtarget->is64Bit()) { if (!Subtarget->is64Bit()) {

@ -87,7 +87,7 @@ public:
/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
/// (created by TableGen) for target dependencies. /// (created by TableGen) for target dependencies.
int getDwarfRegNum(unsigned RegNum) const; int getDwarfRegNum(unsigned RegNum, bool isEH) const;
/// Code Generation virtual methods... /// Code Generation virtual methods...
/// ///

@ -101,8 +101,7 @@ X86TargetAsmInfo::X86TargetAsmInfo(const X86TargetMachine &TM) {
DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug"; DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug";
// Exceptions handling // Exceptions handling
if (!Subtarget->is64Bit()) SupportsExceptionHandling = true;
SupportsExceptionHandling = true;
AbsoluteEHSectionOffsets = false; AbsoluteEHSectionOffsets = false;
DwarfEHFrameSection = DwarfEHFrameSection =
".section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support"; ".section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support";

@ -62,7 +62,7 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) {
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, " << " virtual int getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const;\n" << "unsigned Flavour) const;\n"
<< " virtual int getDwarfRegNum(unsigned RegNum) const = 0;\n" << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
<< "};\n\n"; << "};\n\n";