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[RISCV] Update setcc-logic.ll codegen test

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This should have been updated as part of D59753.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357002 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Luis Marques 2019-03-26 15:41:45 +00:00
parent 6db31ea72b
commit b9eb67aedb
1 changed files with 8 additions and 12 deletions
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20
test/CodeGen/RISCV/setcc-logic.ll
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@ -102,26 +102,22 @@ define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind {
define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
; RV32I-LABEL: and_icmps_const_not1bit_diff:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 44
; RV32I-NEXT: xor a1, a0, a1
; RV32I-NEXT: addi a2, zero, 92
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: xori a1, a0, 92
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: xori a0, a0, 44
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_icmps_const_not1bit_diff:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a1, zero, 44
; RV64I-NEXT: xor a1, a0, a1
; RV64I-NEXT: addi a2, zero, 92
; RV64I-NEXT: xor a0, a0, a2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: xori a1, a0, 92
; RV64I-NEXT: snez a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: xori a0, a0, 44
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
%a = icmp ne i32 %x, 44
%b = icmp ne i32 %x, 92