RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-11-26 13:10:42 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge PPC instructions FMRS and FMRD into a single FMR instruction.

Browse Source 
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.

Also allow folding of memory operands on FMRSD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-02-26 21:53:24 +00:00
parent f34ff01a7a
commit baafcbb4db
2 changed files with 11 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -74,8 +74,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC::FMRS || oc == PPC::FMRD ||
oc == PPC::FMRSD) { // fmr r1, r2
} else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
@ -345,10 +344,9 @@ bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (DestRC == PPC::G8RCRegisterClass) {
BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (DestRC == PPC::F4RCRegisterClass) {
BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
} else if (DestRC == PPC::F8RCRegisterClass) {
BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
} else if (DestRC == PPC::F4RCRegisterClass ||
DestRC == PPC::F8RCRegisterClass) {
BuildMI(MBB, MI, DL, get(PPC::FMR), DestReg).addReg(SrcReg);
} else if (DestRC == PPC::CRRCRegisterClass) {
BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
} else if (DestRC == PPC::VRRCRegisterClass) {
@ -689,7 +687,7 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
getUndefRegState(isUndef)),
FrameIndex);
}
} else if (Opc == PPC::FMRD || Opc == PPC::FMRS || Opc == PPC::FMRSD) {
} else if (Opc == PPC::FMR || Opc == PPC::FMRSD) {
// The register may be F4RC or F8RC, and that determines the memory op.
unsigned OrigReg = MI->getOperand(OpNum).getReg();
// We cannot tell the register class from a physreg alone.
@ -739,7 +737,7 @@ bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
else if ((Opc == PPC::OR8 &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
return true;
else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
else if (Opc == PPC::FMR || Opc == PPC::FMRSD)
return true;
return false;

14
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1019,20 +1019,16 @@ let Uses = [RM] in {
}
}
/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
/// FMR is split into 2 versions, one for 4/8 byte FP, and one for extending.
///
/// Note that these are defined as pseudo-ops on the PPC970 because they are
/// often coalesced away and we don't want the dispatch group builder to think
/// that they will fill slots (which could cause the load of a LSU reject to
/// sneak into a d-group with a store).
def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
"fmr $frD, $frB", FPGeneral,
[]>, // (set F4RC:$frD, F4RC:$frB)
PPC970_Unit_Pseudo;
def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
"fmr $frD, $frB", FPGeneral,
[]>, // (set F8RC:$frD, F8RC:$frB)
PPC970_Unit_Pseudo;
def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
"fmr $frD, $frB", FPGeneral,
[]>, // (set F4RC:$frD, F4RC:$frB)
PPC970_Unit_Pseudo;
def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
"fmr $frD, $frB", FPGeneral,
[(set F8RC:$frD, (fextend F4RC:$frB))]>,