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Support unaligned load/store on more ARM targets
This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on Linux and NaCl. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux/NaCl behave sanely). The patch keeps the -arm-strict-align command line option, and adds -arm-no-strict-align. They behave similarly to GCC's -mstrict-align and -mnostrict-align. I originally encountered this discrepancy in FastIsel tests which expect unaligned load/store generation. Overall this should slightly improve performance in most cases because of reduced I$ pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182175 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
JF Bastien
parent
637cb17a3d
commit
bab06ba696
@ -38,9 +38,24 @@ static cl::opt<bool>
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UseFusedMulOps("arm-use-mulops",
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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StrictAlign("arm-strict-align", cl::Hidden,
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cl::desc("Disallow all unaligned memory accesses"));
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enum AlignMode {
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DefaultAlign,
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StrictAlign,
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NoStrictAlign
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};
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static cl::opt<AlignMode>
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Align(cl::desc("Load/store alignment support"),
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cl::Hidden, cl::init(DefaultAlign),
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cl::values(
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clEnumValN(DefaultAlign, "arm-default-align",
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"Generate unaligned accesses only on hardware/OS "
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"combinations that are known to support them"),
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clEnumValN(StrictAlign, "arm-strict-align",
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"Disallow all unaligned memory accesses"),
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clEnumValN(NoStrictAlign, "arm-no-strict-align",
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"Allow unaligned memory accesses"),
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clEnumValEnd));
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ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, const TargetOptions &Options)
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@ -162,10 +177,32 @@ void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
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if (!isThumb() || hasThumb2())
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PostRAScheduler = true;
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// v6+ may or may not support unaligned mem access depending on the system
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// configuration.
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if (!StrictAlign && hasV6Ops() && isTargetDarwin())
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AllowsUnalignedMem = true;
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switch (Align) {
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case DefaultAlign:
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// Assume pre-ARMv6 doesn't support unaligned accesses.
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//
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// ARMv6 may or may not support unaligned accesses depending on the
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// SCTLR.U bit, which is architecture-specific. We assume ARMv6
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// Darwin targets support unaligned accesses, and others don't.
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//
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// ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
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// which raises an alignment fault on unaligned accesses. Linux
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// defaults this bit to 0 and handles it as a system-wide (not
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// per-process) setting. It is therefore safe to assume that ARMv7+
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// Linux targets support unaligned accesses. The same goes for NaCl.
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//
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// The above behavior is consistent with GCC.
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AllowsUnalignedMem = (
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(hasV7Ops() && (isTargetLinux() || isTargetNaCl())) ||
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(hasV6Ops() && isTargetDarwin()));
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break;
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case StrictAlign:
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AllowsUnalignedMem = false;
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break;
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case NoStrictAlign:
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AllowsUnalignedMem = true;
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break;
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}
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// NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
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uint64_t Bits = getFeatureBits();
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@ -270,9 +270,8 @@ public:
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bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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bool isTargetNaCl() const {
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return TargetTriple.getOS() == Triple::NaCl;
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}
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bool isTargetNaCl() const { return TargetTriple.getOS() == Triple::NaCl; }
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bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
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bool isTargetELF() const { return !isTargetDarwin(); }
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bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
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144
test/CodeGen/ARM/fast-isel-align.ll
Normal file
144
test/CodeGen/ARM/fast-isel-align.ll
Normal file
@ -0,0 +1,144 @@
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
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; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
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; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
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; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
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; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
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; Check unaligned stores
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%struct.anon = type <{ float }>
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@a = common global %struct.anon* null, align 4
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define void @unaligned_store(float %x, float %y) nounwind {
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entry:
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; ARM: @unaligned_store
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; ARM: vmov r1, s0
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; ARM: str r1, [r0]
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; THUMB: @unaligned_store
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; THUMB: vmov r1, s0
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; THUMB: str r1, [r0]
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%add = fadd float %x, %y
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%0 = load %struct.anon** @a, align 4
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%x1 = getelementptr inbounds %struct.anon* %0, i32 0, i32 0
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store float %add, float* %x1, align 1
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ret void
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}
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; Doublewords require only word-alignment.
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; rdar://10528060
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%struct.anon.0 = type { double }
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@foo_unpacked = common global %struct.anon.0 zeroinitializer, align 4
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define void @word_aligned_f64_store(double %a, double %b) nounwind {
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entry:
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; ARM: @word_aligned_f64_store
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; THUMB: @word_aligned_f64_store
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%add = fadd double %a, %b
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store double %add, double* getelementptr inbounds (%struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4
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; ARM: vstr d16, [r0]
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; THUMB: vstr d16, [r0]
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ret void
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}
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; Check unaligned loads of floats
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%class.TAlignTest = type <{ i16, float }>
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define zeroext i1 @unaligned_f32_load(%class.TAlignTest* %this) nounwind align 2 {
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entry:
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; ARM: @unaligned_f32_load
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; THUMB: @unaligned_f32_load
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%0 = alloca %class.TAlignTest*, align 4
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store %class.TAlignTest* %this, %class.TAlignTest** %0, align 4
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%1 = load %class.TAlignTest** %0
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%2 = getelementptr inbounds %class.TAlignTest* %1, i32 0, i32 1
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%3 = load float* %2, align 1
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%4 = fcmp une float %3, 0.000000e+00
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; ARM: ldr r[[R:[0-9]+]], [r0, #2]
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; ARM: vmov s0, r[[R]]
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; ARM: vcmpe.f32 s0, #0
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; THUMB: ldr.w r[[R:[0-9]+]], [r0, #2]
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; THUMB: vmov s0, r[[R]]
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; THUMB: vcmpe.f32 s0, #0
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ret i1 %4
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}
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define void @unaligned_i16_store(i16 %x, i16* %y) nounwind {
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entry:
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; ARM-STRICT-ALIGN: @unaligned_i16_store
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; ARM-STRICT-ALIGN: strb
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; ARM-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: @unaligned_i16_store
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; THUMB-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: strb
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store i16 %x, i16* %y, align 1
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ret void
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}
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define i16 @unaligned_i16_load(i16* %x) nounwind {
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entry:
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; ARM-STRICT-ALIGN: @unaligned_i16_load
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; ARM-STRICT-ALIGN: ldrb
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; ARM-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: @unaligned_i16_load
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; THUMB-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: ldrb
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%0 = load i16* %x, align 1
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ret i16 %0
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}
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define void @unaligned_i32_store(i32 %x, i32* %y) nounwind {
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entry:
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; ARM-STRICT-ALIGN: @unaligned_i32_store
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; ARM-STRICT-ALIGN: strb
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; ARM-STRICT-ALIGN: strb
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; ARM-STRICT-ALIGN: strb
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; ARM-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: @unaligned_i32_store
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; THUMB-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: strb
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store i32 %x, i32* %y, align 1
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ret void
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}
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define i32 @unaligned_i32_load(i32* %x) nounwind {
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entry:
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; ARM-STRICT-ALIGN: @unaligned_i32_load
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; ARM-STRICT-ALIGN: ldrb
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; ARM-STRICT-ALIGN: ldrb
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; ARM-STRICT-ALIGN: ldrb
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; ARM-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: @unaligned_i32_load
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; THUMB-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: ldrb
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%0 = load i32* %x, align 1
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ret i32 %0
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}
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@ -1,7 +1,5 @@
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
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; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
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; Very basic fast-isel functionality.
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define i32 @add(i32 %a, i32 %b) nounwind {
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@ -163,67 +161,6 @@ define void @test4() {
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; ARM: str r1, [r0]
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}
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; Check unaligned stores
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%struct.anon = type <{ float }>
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@a = common global %struct.anon* null, align 4
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define void @unaligned_store(float %x, float %y) nounwind {
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entry:
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; ARM: @unaligned_store
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; ARM: vmov r1, s0
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; ARM: str r1, [r0]
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; THUMB: @unaligned_store
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; THUMB: vmov r1, s0
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; THUMB: str r1, [r0]
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%add = fadd float %x, %y
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%0 = load %struct.anon** @a, align 4
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%x1 = getelementptr inbounds %struct.anon* %0, i32 0, i32 0
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store float %add, float* %x1, align 1
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ret void
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}
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; Doublewords require only word-alignment.
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; rdar://10528060
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%struct.anon.0 = type { double }
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@foo_unpacked = common global %struct.anon.0 zeroinitializer, align 4
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define void @test5(double %a, double %b) nounwind {
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entry:
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; ARM: @test5
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; THUMB: @test5
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%add = fadd double %a, %b
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store double %add, double* getelementptr inbounds (%struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4
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; ARM: vstr d16, [r0]
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; THUMB: vstr d16, [r0]
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ret void
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}
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; Check unaligned loads of floats
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%class.TAlignTest = type <{ i16, float }>
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define zeroext i1 @test6(%class.TAlignTest* %this) nounwind align 2 {
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entry:
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; ARM: @test6
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; THUMB: @test6
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%0 = alloca %class.TAlignTest*, align 4
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store %class.TAlignTest* %this, %class.TAlignTest** %0, align 4
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%1 = load %class.TAlignTest** %0
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%2 = getelementptr inbounds %class.TAlignTest* %1, i32 0, i32 1
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%3 = load float* %2, align 1
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%4 = fcmp une float %3, 0.000000e+00
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; ARM: ldr r0, [r0, #2]
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; ARM: vmov s0, r0
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; ARM: vcmpe.f32 s0, #0
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; THUMB: ldr.w r0, [r0, #2]
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; THUMB: vmov s0, r0
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; THUMB: vcmpe.f32 s0, #0
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ret i1 %4
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}
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; ARM: @urem_fold
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; THUMB: @urem_fold
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; ARM: and r0, r0, #31
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@ -233,10 +170,10 @@ define i32 @urem_fold(i32 %a) nounwind {
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ret i32 %rem
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}
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define i32 @test7() noreturn nounwind {
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define i32 @trap_intrinsic() noreturn nounwind {
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entry:
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; ARM: @test7
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; THUMB: @test7
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; ARM: @trap_intrinsic
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; THUMB: @trap_intrinsic
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; ARM: trap
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; THUMB: trap
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tail call void @llvm.trap( )
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@ -244,67 +181,3 @@ entry:
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}
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declare void @llvm.trap() nounwind
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define void @unaligned_i16_store(i16 %x, i16* %y) nounwind {
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entry:
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; ARM-STRICT-ALIGN: @unaligned_i16_store
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; ARM-STRICT-ALIGN: strb
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; ARM-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: @unaligned_i16_store
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; THUMB-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: strb
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store i16 %x, i16* %y, align 1
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ret void
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}
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define i16 @unaligned_i16_load(i16* %x) nounwind {
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entry:
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; ARM-STRICT-ALIGN: @unaligned_i16_load
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; ARM-STRICT-ALIGN: ldrb
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; ARM-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: @unaligned_i16_load
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; THUMB-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: ldrb
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%0 = load i16* %x, align 1
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ret i16 %0
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}
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define void @unaligned_i32_store(i32 %x, i32* %y) nounwind {
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entry:
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; ARM-STRICT-ALIGN: @unaligned_i32_store
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; ARM-STRICT-ALIGN: strb
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; ARM-STRICT-ALIGN: strb
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; ARM-STRICT-ALIGN: strb
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; ARM-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: @unaligned_i32_store
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; THUMB-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: strb
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; THUMB-STRICT-ALIGN: strb
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store i32 %x, i32* %y, align 1
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ret void
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}
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define i32 @unaligned_i32_load(i32* %x) nounwind {
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entry:
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; ARM-STRICT-ALIGN: @unaligned_i32_load
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; ARM-STRICT-ALIGN: ldrb
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; ARM-STRICT-ALIGN: ldrb
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; ARM-STRICT-ALIGN: ldrb
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; ARM-STRICT-ALIGN: ldrb
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; THUMB-STRICT-ALIGN: @unaligned_i32_load
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; THUMB-STRICT-ALIGN: ldrb
|
||||
; THUMB-STRICT-ALIGN: ldrb
|
||||
; THUMB-STRICT-ALIGN: ldrb
|
||||
; THUMB-STRICT-ALIGN: ldrb
|
||||
|
||||
%0 = load i32* %x, align 1
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user